Nanometric scaling steadily increases failure rates, which are particularly acute for ultimate complementary metal–oxide–semiconductor (CMOS) and post-CMOS devices. We previously established an ECC-based method of memory repair that dramatically reduced the cost for high fault rates, and in this article, we establish a repair architecture that further reduces the power cost. Since CAMs are power hungry (as the address of each memory operation is compared with all the tag fields), we use a cache with the following innovations: 1) innovative repair architecture: although a direct-mapped cache and a set-associative cache that employs offset address bits are efficient for performance of CPUs, we show that they are inefficient for memory repair, since the characteristics of the memory words that need to be replaced in memory repair are different from the case of CPUs, and hence, rather than using any of these cache architectures, we establish an innovative memory repair method that uses another cache and an overflow block; 2) this architecture is thousand times more efficient than other approaches to memory repair based on a CAM or cache; 3) we present a yield computation that determines the size of each block of this repair architecture that is needed to achieve any target yield, and we establish this using a novel probabilistic approach, mathematical approaches and algorithms; and 4) at high fault rates, the yield computation is intractable; we make it tractable via an innovative recursive mathematical approach that significantly reduces the number of operations.

Memory system reliability is a serious concern in many systems today and is becoming more worrisome as technology scales, system size grows and the demand of aggressive voltage reduction becomes more stringent. Thus, disposing of memory repair architectures with strong fault tolerance capability at low cost is desirable. In this context, Error Correcting Codes (ECC)-based repair techniques were proposed and offer aggressive reduction of the repair cost for high defect densities. However, an important issue in advanced process nodes is the fact that, single particles induce Single-Event Upsets (SEUs) in neighbor memory cells, thus leading to Multi-Cell Upsets (MCUs) and Multi-Bit Upsets (MBUs), when they occur in the same memory word. In the case of memories, there exist efficient approaches mitigating this kind of MBUs, in particular the use of interleaving. But when a memory is repaired, the impact of MBUs on the circuitry repairing the faulty memory words should also be mitigated. This can be done by using a repair Content Addressable Memory (CAM) having interleaving at its data-words, or else an Offset CAM. In this paper we present and evaluate a novel repair approach that uses the Offset CAM in ECC-based Memory Repair and hence permits the mitigation of the MBUs affecting it.

In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield, as well as during lifetime to increase lifespan. In technologies affected by high defect densities, conventional repair induces very high cost. To reduce it, in previous work we proposed the ECC-based repair scheme, consisting in using the ECC for fixing words comprising a single faulty cell, and self-repair to fix all other faulty words. This approach is of high interest for ultimate CMOS and post-CMOS technologies, where the defect densities are expected to increase significantly, and/or in very-low power designs as very-low voltage sharply increases defect densities. However, we showed recently that, for high defect densities the diagnosis circuitry required for ECC-based repair may induce large cost. In previous work we addressed this issue by means of a new family of memory test algorithms that exhibit the so-called single-read double-fault detection (SRDF) property. The SRDF algorithms resolve the diagnosis issue at no area cost. However, as they are complex and increase test length, in this paper we explore a new diagnosis approach using iterative test execution, which, together with the SRDF test algorithms, provide a set of options enabling efficient tradeoffs in terms of hardware and power costs, and test length.

We illustrate that memory repair for high fault rates allows improving yield, extending circuit life, reducing power, and improving reliability, and can be used to push aggressively the limits of technology scaling. Then we present several new concepts enabling low-cost memory repair for high fault rates, which allow realizing this promise, as well as the resolution of complex theoretical problems for, which is mandatory for making practical these concepts.

In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield. In technologies affected by high defect densities, conventional repair induces very high costs. To reduce it, we can use ECC-based repair, consisting in using the ECC for fixing words comprising a single faulty cell and self-repair to fix all other faulty words. However, as we show in this paper, for high defect densities the diagnosis circuitry required for ECC-based repair may induce very large hardware cost. To fix this issue, we introduce a new family of memory test algorithms that exhibit a property we termed as “single-read double-fault detection”. This approach gains interest in ultimate CMOS and post-CMOS technologies, where the defect densities are expected to increase significantly, and/or in very-low power design, as very-low voltage sharply increases defect densities.

We illustrate that memory repair for high fault rates can be exploited for improving yield, extending lifetime, reducing power, and improving reliability, and consequently can be used to push aggressively the limits of technology scaling. We also present recent advances in low-area and low-power memory repair for high fault rates. As one of our main goals is to use this repair for reducing as much as possible the power dissipation of the memory system, the power dissipation of the repair circuitry should be kept as low as possible. To comply with this constraint, we also propose a repair approach, which further reduces the power dissipation of the repair circuit.

We illustrate that memory repair for high defect densities allows improving yield, extending circuit life, reducing power, and improving reliability, and can be used to push aggressively the limits of technology scaling. Then we present several developments enabling low-cost memory repair for high defect densities, which alllow realising this promise.

Nanometric scaling steadily increases failure rates, which are expected to be exacerbated as we are approaching the ultimate limits of CMOS and to worsen yet as we will engage in post-CMOS technologies. Moving towards ultimate CMOS and post CMOS also requires increasingly aggressive power reduction. An efficient way to reduce power consists in reducing voltage. Aggressive voltage reduction will result in increasing the numbers of weak memory cells that will operate falsely. Thus, it is desirable to dispose memory repair architectures able to cope with high defect densities. At the same time, reliability is another major concern with aggressive technology scaling. In this context, recent techniques combining memory repair architectures with ECC were able to aggressively reduce repair cost for high defect densities. However, even under the drastic cost reduction obtained with these approaches, power penalty can still be significant as we consider increasing levels of defect density. This paper proposes new repair architectures that are advantageously combined with the previously proposed solutions and allow drastic reduction of dissipated power.

Embedded memories occupy the largest part of modern SoCs and include an even larger amount of transistors. As memories are designed very tightly to the technology limits, they are more prone to failures than other circuits. Thus, they concentrate the large majority of fabrication defects affecting yield adversely. Defect densities are expected to sharply increase in ultimate CMOS and post CMOS processes, resulting in high defect densities. These problems will further worsen due to stringent low-power constraints requiring drastic reduction of voltage levels. To cope with the resulting high defect densities in cost effective manner, ECC-based repair combining ECC with spare words becomes mandatory. On the other hand, coping with accelerating aging may require testing the memories during application execution, making mandatory transparent BIST Nevertheless, traditional implementations of transparent BIST do not comply with the constraints of ECC-based repair. To cope with this issue the paper proposes a transparent BIST architecture compliant with ECC-based repair.

In modern SoCs embedded memories should be repaired to achieve acceptable yield. They should also be protected by ECC against field failures to achieve acceptable reliability. In technologies affected by high defect densities, conventional repair induce very high costs. To reduce them, we can use ECC to fix words comprising a single faulty cell and repair to fix all other faulty words. However it was shown that, for high defect densities, the diagnosis required for ECC-based repair may induce very large cost. In previous work this issue was fixed by means of new memory test algorithms that exhibit the so-called “single-read double-fault detection” property. As these algorithms are complex and increase test length, we explore a new iterative diagnosis approach, which provides tradeoffs in terms of hardware cost and test length.

In modern SoCs embedded memories should be repaired after fabrication to achieve acceptable yield. They should also be protected by ECC against field failures to achieve acceptable reliability. To avoid paying the area and power penalties of both approaches, we can use ECC to fix both fabrication and field failures. However, we show that efficient implementation of this approach may require special diagnosis hardware or new memory test algorithm that exhibit the so-called “single-read double-fault detection” property defined in this paper. We also propose test algorithms satisfying this property.