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Siming Ma

dblp:116/8402 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2021
0000-0002-5138-8127ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Memory systems · 25% Hardware reliability and fault tolerance · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator		 0.412019
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation · MICRO 2019
Hardware reliability and fault tolerance
memory reliability		 0.412019
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation · MICRO 2019
Hardware accelerators and domain-specific architectures › edge accelerator
microcontroller inference		 0.412019
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation · MICRO 2019
Memory systems
non-volatile memory		 0.412019
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation · MICRO 2019

Methods — techniques the papers use, named apart from their topics

sparse encoding · 0.4
YearPublicationVenuePosition
2021 Large margin metric learning for multi-view vehicle re-identification
Siming Ma
 Neurocomputing3
2019 MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation
abstract
Deeply embedded applications require low-power, low-cost hardware that fits within stringent area constraints. Deep learning has many potential uses in these domains, but introduces significant inefficiencies stemming from off-chip DRAM accesses of model weights. Ideally, models would fit entirely on-chip. However, even with compression, memory requirements for state-of-the-art models make on-chip inference impractical. Due to increased density, emerging eNVMs are one promising solution.
Lillian Pentecost, Marco Donato, Brandon Reagen, Udit Gupta 0001, Siming Ma, Gu-Yeon Wei, David Brooks 0001
 MICRO5