This work presents a 16MHz on_chip oscillator based on a frequency_locked loop (FLL) which is radiation hardened by design and intended for space applications. The oscillator maintains a high temperature stability over a wide range oftemperatures, process and voltage variations. The FLL presents a 7-stage current starved ring oscillator using output signal combiners for lower radiation sensitivity. Furthermore, the system presents high reconfigurability by using several DACs to adjust the oscillator’s output frequency and the temperature slope dependency. This reconfigurability is especially useful to maintain all performances across PVT variations.

This paper presents fuzzy c-means-based yield estimation (FUZYE), a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy c-means (FCMs) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems and the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a k-means-based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy.

In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

This paper presents the study and implementation of a new efficient yield optimization technique for multi-objective optimization-based automatic analog integrated circuit sizing. The approach uses a commercial electrical simulator and standard process design kit (PDK) models to perform, during the optimization process, the same Monte Carlo (MC) simulations that designers use. The proposed yield estimation technique reduces the number of required MC simulations by using the k-means algorithm, with a variable number of clusters, to select only a handful potential solutions where the MC simulations are performed. Due to the use of a commercial simulator tool and foundry supplied PDK models the developed methodology provides the most accurate and reliable results, and also, the variable k-means algorithm is able to achieve 91% reduction in the total number of the MC simulations required for an optimization, when considering MC simulations for all solutions. Moreover, this new approach presents a 50% increase in speed performance when comparing to a previous yield optimization technique also using k-means and MC simulations.

In this paper an innovative routing methodology considering wiring symmetry (WS) for multiport multiterminal (MP/MT) signal nets of analog and mixed-signal integrated circuits (ICs) is presented. In our work, first, an electromigration (EM)-aware wiring topology for each power and signal network is constructed directly from the netlist, and then, several embedded symmetry rules between wires are automatically identified and applied in the global and detailed routing phases. The use of such MP terminals strongly enhances both the ability to route the circuit and the WS. The design flow is demonstrated for the UMC 130nm design process.

This paper describes an electromigration-aware and IR-Drop avoidance routing approach considering multiport multiterminal (MP/MT) signal nets of analog integrated circuits (IC). The effects of current densities and temperature in the interconnects may cause the malfunction/failure of a circuit due to IR-Drop or electromigration (EM). These become increasingly more relevant with the ongoing reduction of circuit sizes caused by the evolution of the nanoscale integration processes. Therefore, EM and IR-Drop effects must be taken into account in the design of both power networks and signal wires of analog and mixed-signal ICs, to make their impact on the circuits' reliability negligible. In previous EM and IR-Drop-aware analog IC routing approaches, `dot-models' are assumed for the terminals, i.e., each terminal has only one port that need to be routed, however, in practice, analog standard cells usually contain multiple electrically-equivalent locations, often distributed over different fabrications layers, where legal connections can be made, i.e., MP terminals, which need to be properly explored. The design flow is detailed, and the applicability of the approach is demonstrated with experimental results, and also, by generating the routing of an analog circuit structure for the UMC 130 nm design process.

Typically the design of oscillators is done aiming at both minimum phase noise and minimum power consumption, however, these two objectives are contradictory. Yet, this tradeoff, which is also the base for the definition of the figure of merit of oscillators, is seldom explored is previous publications. In this paper, an LC-Voltage Controlled Oscillator (VCO) was considered in a multi-objective optimization process, where the accuracy and reliability of the solution is guaranteed by the usage of a circuit simulator to evaluate the circuit performance. The state-of-the-art circuit optimization tool AIDA-C was used in the automatic synthesis of the LC-VCO, obtaining a set of about 40 design solutions with FOM bellow -191 dBc/Hz, where the power consumption varies from 0.22 to 0.46 mW and the phase noise varies from -120.47 to -116.72 dBc/Hz.

In the state-of-the-art on analog integrated circuit (IC) automatic routing approaches it is assumed that each terminal has only one port that can be routed, however, in practice a device usually contains multiple electrically-equivalent locations where the connection can be made, multi-port terminals, which are not properly explored. This paper describes an innovative evolutionary approach with multi-port multiterminal (MP/MT) nets for analog IC automatic routing. The netlist and the multi-port terminals are modeled in a Group-Steiner problem that is solved by the Global Router, to obtain the terminal-to-terminal connectivity, and then, for the detailed routing, an optimization kernel is used, namely, an enhanced version of the multi-objective evolutionary algorithm NSGA-II. The Router starts by a single-net procedure, and culminates in a process where all nets are optimized simultaneously. The technology design rules are verified during the evolutionary generation using an in-loop built-in layout evaluation procedure. The automatic routing generation is detailed, and demonstrated for the generation of the layout of a typical analog circuit, for the UMC 130nm design process. The automatically generated layouts are validated using the industrial grade Calibre®tool and the performances of the extracted circuits are compared with the ones achieved in the circuit-level design.

This paper presents a new computational finance approach, combining a Symbolic Aggregate approXimation (SAX) technique together with an optimization kernel based on genetic algorithms (GA). The SAX representation is used to describe the financial time series, so that, relevant patterns can be efficiently identified. The evolutionary optimization kernel is here used to identify the most relevant patterns and generate investment rules. The proposed approach was tested using real data from S&P500. The achieved results show that the proposed approach outperforms both B&H and other state-of-the-art solutions.