Abstract The Fieldbus approach in today’s automation networks represents a significant step toward decentralization, enabling data preprocessing within field devices. Combined with real-time microcontroller response, this capability improves the control process and reduces the computational load on centralized automation controllers. This enables easy remote configuration of devices that require advanced device communication beyond standard data exchange. Reading and updating data from Modbus devices involves the use of polling, a technique that repeatedly scans the registers of each device. The scientific and practical contributions realized in the field of industrial communication on distributed systems are given by highlighting the scenarios in which Modbus devices are integrated and transactions on the communication bus for reading a fixed number of registers located at consecutive addresses, and the improvement enabled by the Modbus Extension (ModbusE) protocol. Based on the proposed mathematical model, with the equations customized for the current scenario, the practical results show the update times of the values on a device that has a maximum number of 50 addresses of the holding register and that are located at consecutive addresses. The results obtained by the authors of this article are presented through the analysis of Modbus transmission and the advantages proposed by ModbusE.

Actual trends in the real-time system field consists of migration towards complex central processing unit (CPU) architectures with enhanced execution predictability and rapid CPU contexts switch, thus obtaining high-performant control systems. The main objective of this paper is to present the results obtained following the implementation of real-time operating systems (RTOS) functions in hardware. Based on the CPU resource multiplication concept, actual researches has been focused on synthesizing in field-programmable gate array (FPGA) and implementing innovative solutions to improve RTOS performance. The results are materialized by validating an efficient hardware scheduler micro-architecture, from which a remarkable efficiency and a plus of performance and predictability are obtained. The experimental results, the FPGA resource requirements for implementation of the processor in different configurations, and the comparisons with other similar processor architectures are presented in order to verify theoretical aspects proposed through this paper.

Task switching, synchronization, and communication between processes are major problems for each real-time operating system. Software implementation of the specific mechanisms may lead to significant delays that can affect deadline requirements for some applications. This paper presents a hardware scheduler architecture integrated into the CPU structure that uses resource remapping techniques for the pipeline registers and for the CPU working registers. We present an original implementation of the hardware structure used for static and dynamic scheduling of the task, unitary management of events, access to architecture shared resources, event generation, and a method used for assigning interrupts to tasks that insures an efficient operation in the context of real-time control. One assembler instruction is used for simultaneous task synchronization with multiple event sources. This architecture allows a task switching time of one clock cycle (with a worst case scenario of three clock cycles for special instructions used for external memory accesses) and a response time of only 1.5 clock cycles for the events. Some mechanisms for improving program execution speed are also taken in consideration.

The article aims to describe an algorithm for dynamic distribution of tasks in a parallel computing system consisting of a network of 9 PlayStation3 (PS3) stations. Due to the fact that the SPU cores do not have units of double precision calculation, these calculations require a longer time. Therefore, an unbalanced distribution of computing tasks on a heterogeneous cluster system as 9×PS3 is necessary. The algorithm produces an estimation of the value of π by calculating the integral $\pi= \int_{0}^{1} \frac{4}{1+x^{2}}$ and makes PPU-SPU empirical distribution of tasks on a smaller number of intervals. After determining the optimum loading between cores 18×PPU (PowerPC Unit) and 54×SPU (Synergetic Processor Unit), the integral calculation algorithm goes to a larger number of intervals.