Multi-Access Point Collaboration (MAPC) envisioned in future Wi-Fi standards has the potential to provide reliable connectivity for time-critical IoT applications. The joint transmission (JT) concept strengthens the signals at the station transmitted from distributed APs, increasing its resilience against interference and multi-path fading to improve reliability and latency performance. There is no commercially available WiFi device capable of doing this since individual APs must be synchronized for time, RF carrier and packet data, and are required to share the medium access with each other. We present an experimental study of distributed dual-AP Wi-Fi network prototype with SDR platforms with openwifi. By synchronizing the clock source, packet transmission control and data, we demonstrate a successful constructive overlap of transmitted WiFi signals at the receiver from distributed APs. Specifically, we observe a 6 dB received signal power gain and a 4.4 dB SNR improvement from the decoded packets with two APs compared to a standalone transmission in the experiment.

Time-Sensitive Networking (TSN) ensures reliable traffic delivery in industrial automation, multimedia, and automotive systems. While effective in wired networks, wireless TSN (WTSN) faces challenges like delays and interference, complicating traffic scheduling. This paper presents a data-driven approach to improve WTSN management by addressing the residual service time (RST) problem, which increases link latency. Tested in a Wi-Fi TSN-based environment, the proposed WTSN digital twin framework preserves TSN traffic guarantees while significantly reducing RST and hence link latency.

Time-Sensitive Networking (TSN) plays a crucial role in ensuring determinism and low latency, vital for the demands of industrial applications. Integrating the benefits of wire-less networks, including mobility, presents a significant challenge in such environments. In this study, we propose a novel solution to address this challenge by introducing handover capabilities into wireless Time-Sensitive Networking (W-TSN). Through real-world development and testing, we present an optimized approach for minimizing handover delay and leveraging machine learning to select the optimal handover time and space moment in a two-dimensional environment, with low effect on time-sensitive traffic. Our findings demonstrate that our mechanism reduces handover delay below 10 milliseconds and optimizes the handover moment selection, leading to improvements in critical network parameters such as bandwidth and jitter.

With ever-increasing throughput-hungry applications running over WiFi, such as Virtual and eXtended Reality (VR/XR), on the one hand and the need for deterministic communication on the other, network densification is not an option. With dense network deployment interference between overlapping basic service set (OBSS) become the main source of system throughput drop and packet delays, decreasing the benefits of dense network. With the latest WiFi 7 standard being standardized, access point (AP) coordination is one of the key features foreseen to be added. With increased interactions between APs from different OBSS, spatial reuse feature can benefit in determining accurately the levels of interference and modulation and coding scheme (MCS) index to be used for concurrent transmissions. In this paper we show a centralized Coordinated Spatial Reuse (C-SR) algorithm implemented in the network controller that determines the transmit powers of the concurrent AP transmitters based on calculated interference levels in the main receiver. In addition, the algorithm determines the MCS index for each concurrent transmission. In a test-bed measurement setup, we show that the overall system goodput is increased by 20% and 33%, respectively, for the network topology where receivers are positioned in the inner zone between APs. In addition, the communication latency is maintained below certain threshold, compared to cases where C-SR is not activated.

Field-Programmable Gate Array (FPGA)-based Software-Defined Radio (SDR) is well-suited for experimenting with advanced wireless communication systems, as it allows to alter the architecture promptly while obtaining high performance. However, programming the FPGA using a Hardware Description Language (HDL) is a time-consuming task for FPGA developers and difficult for software developers, which limits the potential of SDR. High-Level Synthesis (HLS) tools aid the designers by allowing them to program on a higher layer of abstraction. However, if not carefully designed, it may lead to a degradation in computing performance or significant increase in resource utilization. This work shows that it is feasible to design modern Orthogonal Frequency Division Multiplex (OFDM) baseband processing modules like channel estimation and equalization using HLS without sacrificing performance and to integrate them in an HDL design to form a fully-operational FPGA-based Wi-Fi (IEEE 802.11a/g/n) transceiver. Starting from no HLS experience, a design with limited overhead in terms of latency and resource utilization as compared to the HDL approach was created in less than one month. The FPGA design generated by HLS achieved the same performance as compared to its HDL counterpart when deployed on a System-on-Chip (SoC)-based SDR, as verified by a professional wireless connectivity tester.

End-to-end low-latency deterministic communication, next to high-reliability communication, is one of the key features that communication systems are expected to provide for industrial systems. To achieve time-sensitive networking (TSN), a set of standards have already been designed and deployed for wired industrial communication systems, coexisting or replacing other long-living technologies such as Fieldbus, Profibus, or Modbus. Wireless time-sensitive networking (W-TSN) is getting traction with the development of the newest WiFi generation (IEEE 802.11be) as well as advances in cellular networking. One of the challenges in W-TSN is scheduling and isolation of time-critical traffic in the shared wireless medium. In this paper we present a solution, called dynamic traffic classification, to give faster dedicated access to the wireless medium for packets of highly-time-sensitive flows, that can be generated randomly. Dynamic traffic classification utilizes so-called shadow queues implemented in FPGA-based WiFi baseband SDR platform, openwifi, to prioritize channel access of certain packets over others. We show that the channel access latency in the case of dynamic traffic classification does not depend on the scheduling cycle, but on the distribution of dedicated time slots inside the schedule cycle. As such we achieve to decrease the end-to-end latency by 75% in case of longer communication cycles with wider space between communication time slots.

Investigating the security of Wi-Fi devices often requires writing scripts that send unexpected or malformed frames, to subsequently monitor how the devices respond. Such tests generally use Linux and off-the-self Wi-Fi dongles. Typically, the dongle is put into monitor mode to get access to the raw content of received Wi-Fi frames and to inject, i.e., transmit, customized frames. In this paper, we demonstrate that monitor mode on Linux may, unbeknownst to the user, mistakenly inject Wi-Fi frames or even drop selected frames instead of sending them. We discuss cases where this causes security testing tools to misbehave, making users to believe that a device under test is secure while in reality it is vulnerable to an attack. To remedy this problem, we create a script to test raw frame injection, and we extend the Radiotap standard to gain more control over frame injection. Our extension is now part of the Radiotap standard and has been implemented in Linux. We tested it using commercial Wi-Fi dongles and using openwifi, which is an open implementation of Wi-Fi on top of software-defined radios. With our improved setup, we reproduced tests for the KRACK and FragAttack vulnerabilities, and discovered previously unknown vulnerabilities in three smartphones.

Software Defined Radio (SDR) platforms are valuable for research and development activities or high-end systems that demand real-time adaptable wireless protocols. While low latency can be achieved using the dedicated digital processing unit of a state-of-the-art SDR platform, its Radio Frequency (RF) front-end often poses a limitation in terms of turnaround time (TT), the time needed for switching from the receiving to the transmitting mode (or vice versa). Zero Intermediate Frequency (ZIF) transceivers are favorable for SDR, but suffer from self-interference even if the device is not currently transmitting. The strict MAC-layer requirements of Time Division Duplex (TDD) protocols like Wi-Fi cannot be achieved using configurable ZIF transceivers without having to compromise receiver sensitivity. Using a novel approach, we show that the TT using the AD9361 RF front-end can be as low as 640 ns, while the self-interference is at the same level as achieved by the conventional TDD mode, which has a TT of at least 55 μs. As compared to Frequency Division Duplex (FDD) mode, a decrease of receiver noise floor by about 13 dB in the 2.4 GHz band and by about 4.5 dB in the 5 GHz band is achieved.

Precision time protocol (PTP), a state-of-the-art clock synchronization protocol primarily designed for wired networks, has recently gained attention in the wireless community, due to the increased use of the IEEE 802.11 wireless local area networks (WLAN) in real-time distributed systems. However, all the existing WLAN-based PTP designs either incorporate software timestamping (TS) delivering poor clock synchronization accuracy, or hardware (HW) TS providing better synchronization accuracy at the cost of a significant amount of HW overhead. Moreover, the performance of the existing PTP solutions is mostly evaluated in single-hop wireless networks, while the performance across wired and wireless networks is taken for granted. In this article, a new software-defined-radio-based approach to implement PTP is introduced and validated for the IEEE 802.11 WLAN. Instead of using a dedicated HW clock, the solution utilizes the timing synchronization function clock, an existing clock in the IEEE802.11 standard for synchronization between access point and WLAN stations. The performance of the proposed solution is first investigated within a single-hop WLAN and then across wired–wireless networks. Experimental results unveil that 90% of the absolute clock synchronization error falls within 1.4$\mu \mathrm{s}$.

CSI (Channel State Information) of WiFi systems contains the environment channel response between the transmitter and the receiver, so the people/objects and their movement in between can be sensed. To get CSI, the receiver performs channel estimation based on the pre-known training field of the transmitted WiFi signal. CSI related technology is useful in many cases, but it also brings concerns on privacy and security. In this paper, we open sourced a CSI fuzzer to enhance the privacy and security of WiFi CSI applications. It is built and embedded into the transmitter of openwifi, which is an open source full-stack WiFi chip design, to prevent unauthorized sensing without sacrificing the WiFi link performance. The CSI fuzzer imposes an artificial channel response to the signal before it is transmitted, so the CSI seen by the receiver will indicate the actual channel response combined with the artificial response. Only the authorized receiver, that knows the artificial response, can calculate the actual channel response and perform the CSI sensing. Another potential application of the CSI fuzzer is covert channels based on a set of pre-defined artificial response patterns. Our work resolves the pain point of implementing the anti-sensing idea based on the commercial off-the-shelf WiFi devices.

Collision detection (CD) is a key capability of carrier sense multiple access (CSMA) based medium access control (MAC) protocol. Applying CD, the transmitter can abort transmission immediately so that the power can be saved. This technique does not need the peer receiver to give feedback on whether there is a packet collision, and hence, the overall overhead is significantly low. The challenge, however, is to operate in transmit time and instantly detect the week colliding signal in the presence of strong self-interference (SI). This paper investigates two CD methods. The first technique trains a convolutional neural network (CNN) model which operates on raw baseband samples, without the need for pre-decoding. The second method treats the SI as a normal signal and estimates the signal to noise ratio (SNR): low SNR implies there is a collision because the pure SI is expected to have high SNR. Both models are evaluated by IEEE 802.15.4-like measured and simulated signals. The results show that collisions up to 30 dB below the SI signal can be detected precisely within 20 μs, while the proposed models can deliver acceptably low false alarm rate <; 1.5 %.

This paper introduces a Non-Orthogonal Multiple Access (NOMA) scheme to support concurrent transmission of multiple IEEE 802.15.4 packets. Unlike collision avoidance Multiple Access Control (MAC), concurrent transmission supports Concurrent-MAC (C-MAC) where packet collision is allowed. The communication latency can be reduced by C-MAC because a user can transmit immediately without waiting for the completion of other users' transmission. The big challenge of concurrent transmission is that error free demodulation of multiple collided packets hardly can be achieved due to severe Multiple Access Interference (MAI). To improve the demodulation performance with MAI presented, we introduce an architecture with multiple switching antennas sharing a single analog transceiver to capture spatial character of different users. Successive Interference Cancellation (SIC) algorithm is designed to separate collided packets by utilizing the spatial character. Simulation shows that at least five users can transmit concurrently to the SIC receiver equipped with eight antennas without sacrificing Packet Error Rate.

Open source Software Defined Radio (SDR) project, such as srsLTE and Open Air Interface (OAI), has been widely used for 4G/5G research. However the SDR implementation of the IEEE802.11 (Wi-Fi) is still difficult. The Wi-Fi Short InterFrame Space (SIFS) requires acknowledgement (ACK) packet being sent out in 10μs/16μs (2.4GHz/5GHz) after receiving a packet successfully, thus the Personal Computer (PC) based SDR architecture hardly can be used due to the latency (≥ 100μs) between PC and Radio Frequency (RF) front-end. Researchers have to do simulation, hack a commercial chip or buy an expensive reference design to test their ideas. To change this situation, we have developed an open-source full-stack IEEE802.11a/g/n SDR implementation - openwifi. It is based on Xilinx Zynq Systemon-Chip (SoC) that includes Field Programmable Gate Array (FPGA) and ARM processor. With the low latency connection between FPGA and RF front-end, the most critical SIFS timing is achieved by implementing Physical layer (PHY) and low level Media Access Control (low MAC) in FPGA. The corresponding driver is implemented in the embedded Linux running on the ARM processor. The driver instantiates Application Programming Interfaces (APIs) defined by Linux mac80211 subsystem, which is widely used for most SoftMAC Wi-Fi chips. Researchers could study and modify openwifi easily thanks to the modular design. Compared to PC based SDR, the SoC is also a better choice for portable and embedded scenarios.

Mobile traffic demand is expected to grow as much as eight-fold in the coming next five years, putting strain in current wireless infrastructures . Meanwhile the diversity of traffic and standards may explode as well. One of the most common means for matching these mounting requirements is through network densification , essentially increasing the density of deployment of operators’ base stations in many small cells and handling timing critical traffic at the edge. In this paper we take a step in that direction by implementing a virtualized small cell base station consisting of multiple, isolated LTE PHY stacks running concurrently on top of a hypervisor deployed on a cheap, off-the-shelf x86 server and a shared radio head. In particular, we show that it is possible to run multiple virtualized base stations while achieving throughput equal or close to the theoretical maximum. In contrast to C-RAN (Cloud/Centralized Radio Access Network), our virtualized small cell base station has full stack at the edge so that a low latency high throughput front-haul, which is necessary in C-RAN architecture, is not needed. This approach brings all the flexibility and configurability (from network management point of view) that a software based implementation provides while the transparent architecture enables the possibility of multiple standards sharing the same radio infrastructure.

Spectrum scarcity has been driving cellular operators to utilize unlicensed spectrum in conjunction with licensed bands to deliver mobile data to its Long-Term Evolution (LTE) users, offloading the fully allocated LTE bands. However, the use of LTE in unlicensed spectrum creates numerous challenges as the fair coexistence with other technologies. A myriad of experimental works tackles the problems involved in the coexistence of different radio access technologies (RAT) in unlicensed spectrum, however, they do not cover all aspects of the problem and fail to provide the framework adopted in the experiments for reproducible research. Therefore, in this demo we present a highly configurable packetized-LTE PHY open-source framework for coexistence experiments. The framework allows the evaluation and comparison of different coexistence techniques.

Wireless network deployments in industry often grow organically with new technologies added over time, among which many use the non-licensed spectrum to avoid licensing costs. As a result, technologies competing for the same spectrum end up deployed in the same area, causing coexistence problems to manifest themselves at a later stage. To avoid unexpected performance degradation, there is a need to evaluate the impact of additional wireless technologies on an existing network before the actual deployment. This paper proposes to simplify the impact assessment by emulating the signals of the potential wireless network with a single software-defined radio. To evaluate the emulator's performance, the impact of Bluetooth on Wi-Fi technology is considered as the reference scenario. A series of real-life experiments with configurable traffic load and network scale are conducted to estimate the impact of Bluetooth network on a Wi-Fi link, and the corresponding measurements are repeated with the emulated Bluetooth signals. To the best of the authors' knowledge, we are the first to propose such a solution, and it is shown that the use of our emulator gives a reliable indication of the expected impact at the location of the Wi-Fi link. As such, this paper provides an important step toward a simple, cost efficient, and reliable solution, to assess the impact of a wireless network prior to its deployment.

A standard-throughput-approaching LDPC decoder has been implemented on a mid-range GPU in this paper. Turbo-Decoding Message-Passing algorithm is applied to achieve high throughput. Different from traditional host managed multi-streams to hide host-device transfer delay, we use kernel maintained data transfer scheme to achieve implicit data transfer between host memory and device shared memory, which eliminates an intermediate stage of global memory. Data type optimization, memory accessing optimization, and low complexity Soft-In Soft-Out algorithm are also used to improve efficiency. Through these optimization methods, the 802.11n LDPC decoder on NVIDIA GTX480 GPU, which is released in 2010 with Fermi architecture, has achieved a high throughput of 295Mb/s when decoding 512 codewords simultaneously, which is close to highest bit rate 300Mb/s with 20MHz bandwidth in 802.11n standard. Decoding 1024 and 4096 codewords achieve 330 and 365Mb/s. A 802.16e LDPC decoder is also implemented, 374Mb/s (512 codewords), 435Mb/s (1024 codewords) and 507Mb/s (4096 codewords) throughputs have been achieved.

Parallel implementations of Turbo decoding has been studied extensively. Traditionally, the number of parallel sub-decoders is limited to maintain acceptable code block error rate performance loss caused by the edge effect of code block division. In addition, the sub-decoders require synchronization to exchange information in the iterative process. In this paper, we propose loosening the synchronization between the sub-decoders to achieve higher utilization of parallel processor resources. Our method allows high degree of parallel processor utilization in decoding of a single code block providing a scalable software-based implementation. The proposed implementation is demonstrated using a graphics processing unit. We achieve 122.8Mbps decoding throughput using a medium range GPU, the Nvidia GTX480. This is, to the best of our knowledge, the fastest Turbo decoding throughput achieved with a GPU-based implementation.

Turbo coding is commonly used in the current wireless standards such as 3G and 4G. However, due to the high computational requirements, its software-defined implementation is challenging. This paper proposes a static multi-issue exposed datapath processor design tailored for turbo decoding. In order to utilize the parallel processor datapath efficiently without resorting to low level assembly programming, the turbo decoder is implemented using OpenCL, a parallel programming standard for heterogeneous devices. The proposed implementation includes only a small set of Turbo-specific custom operations to accelerate the most critical parts of the algorithm. Most of the computation is performed using general-purpose integer operations. Thus, the processor design can be used as a general-purpose OpenCL accelerator for arbitrary integer workloads as well. The proposed processor design was evaluated both by implementing it using a Xilinx Virtex 6 FPGA and by ASIC synthesis using 130 nm and 40 nm technology libraries. The implementation achieves over 63 Mbps Turbo decoding throughput on a single low-power core. According to the ASIC synthesis, the maximum operating clock frequency is 344 MHz/1 050 MHz (130 nm/40 nm).