This design contest document proposes a low quiescent current low-dropout regulator (LDO) with an auxiliary amplifier, flipped voltage follower (FVF)-based power supply rejection ratio enhanced circuit (FBPEC) for electroencephalogram (EEG) recording devices. A FVF filter, current mirror, and common-source amplifier are employed to configure the FBPEC. The FBPEC employs the characteristics of the FVF filter to reduce the current consumption and increase the gain at specific frequencies. A 0.18 μm CMOS process is used to design and fabricate the proposed LDO. Compared to the general configuration LDO by measurement results, the proposed LDO exhibits an enhanced power supply rejection ratio (PSRR) up to 18 dB at frequencies exceeding 8 kHz. Moreover, the quiescent current of the proposed LDO at no-load is 648 nA. The proposed LDO exhibits a good figure-of-merit score compared to those of previous works, suggesting that the proposed circuit is an effective solution for use in wearable low-power EEG recording devices.

In this design contest document, measurement results demonstrate the effectiveness of a designed low current consumption amplifier for a compressed-sensing (CS) framework in wearable electroencephalography (EEG) recording devices. When reconstructing with a frequency bases, the reduction of biased 1/f noise is more important than frequency-unbiased white noise. Therefore, we designed an amplifier that reduces 1/f noise rather than white noise, while reducing power consumption, and employed it in the system. The designed amplifier is based a capacitively coupled chopper instrumentation amplifier (CCIA) architecture which used for low-noise amplifier (LNA). According to measurements of the designed CCIA, the power consumption is 0.36 μW/channel, it has the lower power consumption compared to amplifiers designed for similar applications in the past. The input referred noise (IRN) excluding the hum of the power supply was 3.3 μVrms. The measured IRN and simulations were used to confirm the effect of noise from CCIA on the CS-based EEG measurement framework. The difference in the normalized mean squared error at CR = 4 to the uncompressed conditions is 0.008. This result shows that even with the LNA specialized for low power consumption, a slight signal degradation is observed when the compression ratio is increased up to 4 in the CS framework by making use of the sparsity of EEG in the frequency domain.

Achieving power savings while maintaining accuracy is essential for wireless electroencephalogram (EEG) measurement devices, enabling them to be lighter with smaller batteries and longer operating times. To meet this requirement, we developed a wireless EEG transmission system that utilizes compressed sensing (CS) with random undersampling to achieve high-accuracy reconstruction while reducing sensing and transmission power. As a key feature of the implemented system, we designed and employed a suitable basis from previously obtained EEG signals for the block sparse Bayesian learning algorithm. Measurements showed that our system achieved significant power savings with a compression ratio of 6, consuming only 72 µW, which is lower than that reported in the latest CS-based study. Notably, despite the reduced power consumption, we reduced the normalized mean square error to 0.116, achieving more than twice the reconstruction accuracy reported in the previous study.

This study presents a solution to achieve low power consumption by the intermittent operation of low-noise amplifiers (LNAs) for wireless electroencephalographs, that need a smaller battery. The LNA operates intermittently synchronized with the sampling timing of the analog-to-digital converter (ADC) by using the random undersampling matrix utilized in a previously proposed compressed sensing (CS) electroencephalogram measurement system. Designed using a 0.18 μm CMOS process, the LNA includes an intermittent operation circuit. The simulation results, the start-up time of the LNA was set to 4ms and the intermittent operation was performed at compression ratio of 4.17 based on a sampling frequency of 200Hz. The intermittent operation reduced power consumption by 58% compared to constant operation. The normalized mean square error (NMSE) was used to evaluate the influence of intermittent LNA operation on the reconstruction accuracy of CS. The difference in NMSE between intermittent and constant operation was only 9% on average over 25 frames. This indicates that intermittent operation minimally influenced the reconstruction accuracy.

This paper presents an extremely low-voltage flip-flop (ELVFF) consisting of recursive stacking body-bias logic gates with the capability of operating at extremely low supply voltages. The ELVFF is based on a conventional NAND latch based flip-flop (NLFF), and consists of three-times-recursive-stacking body-bias NANDs (3RSBB-NANDs) and onetime-recursive-stacking body-bias inverters (1RSBB-INVs). The recursive-stacking and body-bias techniques provide an effective strategy for achieving ELV operation. The combination of these techniques allows for the enhancement of both the voltage gain and voltage swing of logic gates, thereby enabling the ELVFF to operate at extremely low supply voltages. Simulation results in a standard 180-nm CMOS process with a deep-n-well option indicated that our proposed ELVFF was capable of operating at an extremely low supply voltage of 40 mV. Measurement results also demonstrated that the ELVFF stored and maintained the correct logic with an amplitude of 27 mV and a power dissipation of 6.03 nW at a 39-mV power supply. The ELVFF is suitable for sub-100-mV ELV applications, such as energy harvesting, at the cost of an increased number of transistors, area, power, and delay time.

The application of compressed sensing has gained interest for its potential to achieve low power consumption in wireless electroencephalogram (EEG) measurement devices. In this study, we propose a system that utilizes the EEG basis (EEGB) matrix, allowing for the same reconstruction accuracy as a discrete cosine transform (DCT) matrix, which is a well known conventional matrix, while realizing low-power consumption in a low noise amplifier (LNA). Our theoretical analysis reveals that, for a 5x compression aiming at an equivalent normalized mean square error of 0.25, the use of the EEGB matrix can decrease the power consumption of the LNA by approximately 75% compared to using a DCT matrix.

This paper presents a programmable differential bandgap reference (DBGR) for ultra-low-power IoT (Internet-of-Things) edge node devices. The circuit consists of a bandgap reference (BGR) based current generator (CG) and differential voltage generator (DVG). The BGR-based CG generates a current and a voltage, and the DVG generates another voltage from the current. A differential voltage reference can be obtained by taking the voltage difference from the voltages. The circuit can produce a programmable output differential voltage by changing the multipliers of MOSFETs in a differential pair and resistance with digital codes. Simulation results demonstrate that the proposed DBGR can generate a 25- to 200-mV reference voltage with a 25-mV step within a ±0.7% temperature inaccuracy in a range from −20 to 100°C. The power was 87 nW. A Monte Carlo simulation showed that the coefficient of the variation in the reference was within 1.1%.

The use of compressed sensing (CS) to achieve low-power consumptions in electroencephalogram (EEG) mea-surement devices has attracted considerable research interest. However, a signal processing issue in utilizing CS is the trade- off between the compression ratio (CR), reconstruction accuracy, and reconstruction time. In this study, we developed a method that resulted in a shortened reconstruction time and a high reconstruction accuracy with a high CR by utilizing selected EEG signals. When EEG signals were sorted using the mean frequency and only the most frequently occurring EEG signals were used in the basis matrix, a compressed EEG signal with an original time length of 1 s could be recovered in only approximately 26 ms, and an average normalized mean square error of 0.11 was achieved at a CR of 5.

The realization of a compact wireless electroencephalogram (EEG) measurement device that can be used in daily life without concern for power consumption has garnered considerable attention. Thus, wireless EEG measurement devices with energy harvesting have been proposed, but there have been issues with harvester size and power output. In this study, we proposed and implemented a wireless EEG measurement device using compressed sensing, utilizing random undersampling and only a$40\ \text{mm}\times 40\ \text{mm}$small thermoelectric generator (TEG) as the power source. The results of the 4x compression experiment revealed a reduction in the power of the microcontroller from$345\ \mu\mathrm{W}$to$97\ \mu\mathrm{W}$at 3.3 V. This implies that a wireless EEG measurement device can operate well with a small TEG, even though the reconstructed signal is not inferior to the original signal, in which the average normalized mean square error is approximately 0.24.

Low-voltage charge pump (CP) and its dedicated multi-stage driver (DRV) for sub-50-mV energy harvesting are proposed. The proposed DRV utilizes the output voltages of each CP to efficiently boost the control clock signals. The boosted clock signals are used as switching signals for each CP and DRV to turn switch transistors on and off. Moreover, reset transistors are added to the DRV to ensure an adequate non-overlapping period between switching signals. Simulated results demonstrated that (i) the proposed DRV can generate boosted clock signals of 712.6 mV from input voltage of 100 mV and (ii) the multi-stage CP can generate output voltage of 702.5-mV. Peak efficiency of the CP is 42.9%. The proposed CP and DRV can operate at extremely low voltage of 41 mV.

This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.

Analog-to-digital (A/D) converter (ADC) and related analog hardware designs are important factors to simplify the transceiver circuits in wireless communication systems. In order to mitigate the nonlinearity of a low-resolution ADC that reduces the required analog hardware complexity, we have investigated two nonlinearity mitigation techniques for A/D conversion, i.e., the dither-ADC and the hysteresis-ADC. In this paper, we evaluate the effect of the nonlinearity mitigated A/D conversion techniques on the achievable performance in single carrier offset-quadrature-amplitude-modulation (OQAM)and QAM systems, where the receiver adopts either the dither-ADC or the hysteresis-ADC. Simulation results prove that both the dither-ADC and the hysteresis-ADC are effective in improving BER performance of both OQAM and QAM systems affected by the nonlinearity of ADC, while the transmitter employs a selected mapping technique that achieves a low peak-to-average power ratio (PAPR).