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Richard Petri 0002

dblp:117/6697-2 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Energy-efficient computing · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
energy-efficient neural network accelerator
0.712023
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration · DAC 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.712023
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration · DAC 2023
Energy-efficient computing
voltage scaling
0.712023
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration · DAC 2023

Methods — techniques the papers use, named apart from their topics

retraining · 0.7
YearPublicationVenuePosition
2023 PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration
abstract
Deep neural networks (DNNs) have been successfully applied in various fields. A major challenge of deploying DNNs, especially on edge devices, is power consumption, due to the large number of multiply-and-accumulate (MAC) operations. To address this challenge, we propose PowerPruning, a novel method to reduce power consumption in digital neural network accelerators by selecting weights that lead to less power consumption in MAC operations. In addition, the timing characteristics of the selected weights together with all activation transitions are evaluated. The weights and activations that lead to small delays are further selected. Consequently, the maximum delay of the sensitized circuit paths in the MAC units is reduced even without modifying MAC units, which thus allows a flexible scaling of supply voltage to reduce power consumption further. Together with retraining, the proposed method can reduce power consumption of DNNs on hardware by up to 73.9% with only a slight accuracy loss.
Richard Petri 0002, Grace Li Zhang, Yiran Chen 0001, Ulf Schlichtmann, Bing Li 0005
DAC1