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EDBT 2026 Demo / reviewers in the wild / expert

Eunhwan Kim

dblp:117/7796 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
0009-0004-4304-0958ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 50% Hardware accelerators and domain-specific architectures · 44% Integrated circuit design · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
DRAM		 0.712023
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time · DAC 2023
Memory systems › DRAM › DRAM architecture
embedded DRAM		 0.712023
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time · DAC 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator
in-memory computing accelerator		 0.712023
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time · DAC 2023
Hardware accelerators and domain-specific architectures
machine learning accelerator		 0.712023
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time · DAC 2023
Integrated circuit design › parasitic capacitance
coupling capacitance		 0.212023
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time · DAC 2023
Memory systems
processing-in-memory		 0.212023
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time · DAC 2023
YearPublicationVenuePosition
2023 In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time
abstract
Logic compatible eDRAM cell-based computing-in-memory (CIM) neural network accelerators have been actively studied as an energy-efficient neural network computing platform thanks to their small cell size and low static power compared to SRAM. However, previous eDRAM-based CIM accelerators suffer from significant accuracy degradation caused by process, voltage, temperature (PVT) variations and short retention time. To overcome the issues, we introduce a PVT-variation tolerant capacitive coupling-based eDRAM cell that has a much longer retention time than previous works. Simulation results show that the proposed eDRAM cell has up to 50× higher retention time compared to the state-of-the-art designs.
Inhwan Lee, Eunhwan Kim, Nameun Kang, Hyunmyung Oh, Jae-Joon Kim
 DAC2