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Navaneeth Jamadagni

dblp:118/0815 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
arithmetic circuit design
0.212015
Radix-2 Division Algorithms with an Over-Redundant Digit Set · IEEE Trans. Computers 2015
Processor architecture and microarchitecture
division algorithm
0.212015
Radix-2 Division Algorithms with an Over-Redundant Digit Set · IEEE Trans. Computers 2015
Integrated circuit design › digital arithmetic circuits
redundant digit representation
0.212015
Radix-2 Division Algorithms with an Over-Redundant Digit Set · IEEE Trans. Computers 2015

Methods — techniques the papers use, named apart from their topics

digit recurrence · 0.2carry-save addition · 0.2
YearPublicationVenuePosition
2015 Radix-2 Division Algorithms with an Over-Redundant Digit Set
abstract
This paper presents a derivation of four radix-2 division algorithms by digit recurrence. Each division algorithm selects a quotient digit from the over-redundant digit set {-2, -1, 0, 1, 2}, and the selection of each quotient digit depends only on the two most-significant digits of the partial remainder in a redundant representation. Two algorithms use a two's complement representation for the partial remainder and carry-save additions, and the other two algorithms use a binary signed-digit representation for the partial remainder and carry-free additions. Three algorithms are novel. The fourth algorithm has been presented before. Results from the synthesized netlists show that two of our fastest algorithms achieve an improvement of 10 percent in latency per iteration over a standard radix-2 SRT algorithm at the cost of 36 percent more power and 50 percent more area.
Jo C. Ebergen, Navaneeth Jamadagni
IEEE Trans. Computers2