Ring oscillators are widely used in modern applications due to their simplicity, compact size, and low power consumption. Their oscillation frequency is determined by the number of stages (or inverters) and the average delay per inverter. In advanced submicron technologies, logic gates’ minimal propagation delay allows high-frequency operation with great efficiency. However, ring oscillators become increasingly power-inefficient at lower frequencies (MHz range). This paper presents a novel oscillator topology that combines two injection locked stacked ring oscillators with different stage counts, generating two output frequencies with a fractional ratio. The stacking technique reuses the supply current while splitting the available supply voltage across the two oscillators. This approach effectively reduces the oscillation frequency while maintaining energy efficiency and improving phase noise performance by approximately 3 dBc/Hz across all frequencies. Simulation results in TSMC 65nm confirm that the locking mechanism of two stacked ring oscillators is achieved, even when they contain different numbers of inverters, enabling fractional injection locking.

Advances in bioelectronic medicine have led to a reduction in implant size and notable improvements in energy management and data transmission techniques. Bulky titanium casings traditionally used to shield implant electronics are being gradually replaced by more streamlined materials, primarily composed of polymers and thin film ceramics. This transition offers numerous advantages, including a smaller form factor, enhanced flexibility, and the facilitation of wireless power and data transmission. However, it is essential to acknowledge potential drawbacks of these innovative encapsulation materials, such as the unknown longevity and adhesion issues that may compromise hermeticity. To investigate the hermeticity and long-term performance of conformal encapsulations, we propose a fully encapsulated wireless monitoring system with novel circuitry. The system comprises energy harvesting, humidity assessment, and passive communication. In this paper, we delve into each of these areas, presenting innovative solutions that are later implemented and tested. The final system is realized in an integrated circuit technology of 65 nm, fitting in a compact area of 0.3 mm2 ($76~\%$occupied by the integrated receiver coil), while consuming$1.3~\mu $W. All the necessary components are fully integrated, allowing for increased miniaturization and lower power consumption.

Cardiovascular diseases are one of the major causes of death worldwide, which drives the research on smart catheters for early diagnosis. Deploying ASICs at the tip of the catheter is challenging, as power is delivered through a long and thin wire, limiting the power integrity. Also, since the catheter needs to fit into the diameter of a blood vessel or other narrow channel in the human body, there is no room for bulky decoupling capacitors. Finally, power consumption must be optimized, as the energy density may lead to prohibitive heating of tissues and fluids. Still, while targeting better performance, e.g. higher imaging resolution, the requirements for bandwidth and accuracy consistently increase, ultimately demanding precise on-chip clock generation for communication and digitization. In this paper we propose a circuit for at-the-tip clock generation in smart catheters, comprising a low-drop out (LDO) regulator, voltage and current references and a low-jitter digitally controlled oscillator (DCO). The clock generator also comprises a clock divider with programmable duty cycle, allowing system reconfiguration. The circuit is laid out and simulated under application conditions. The LDO achieves a full-spectrum power supply ripple rejection (PSRR) of 50 dB with an output load of 10 mA. The DCO, supplied by the aforementioned LDO, achieves a phase noise of -104.5 dBc/Hz at an offset of 1 MHz and 1.25 GHz of oscillating frequency. The proposed clock generator allows digitization at 200 MSps with a maximum SNR of 56.3 dB for an input signal of 50 MHz if phase noise is integrated from 100 kHz to 625 MHz.

Ring oscillators are one of the simplest, smallest and most energy-efficient topologies when it comes to clock generation. Being implemented using a chain of digital inverters, their oscillation frequency can be set by the inverters count in the chain and the delay of each inverter. This is an advantage when considering the simplicity and size, however, it is also the cause for high frequency variation with temperature. In this paper we propose an ultra-low power oscillator circuit that exploits a stack of small ring oscillators for supply current reuse and injection locking, which provides phase noise improvement. Frequency stability is achieved through a feedback loop that relies on a frequency-to-voltage converter with improved linearity and reduced temperature sensitivity based on MOS capacitors. Simulation results show that the oscillation frequency changes ±0.4% from 0 to 70°C (57 ppm/°C) while consuming 2.4 μW at 10 MHz, with a phase noise of -88.9 dBc/Hz at 100 kHz offset.

It is imperative that new solutions in Electronic Design Automation (EDA) appear to cope with the increasing complexity of modern chips. However, the lack of broadly available platforms for rapid application development (RAD) of EDA tools hinders the volume and quality of the contributions from the scientific community. In this paper, we tackle this issue by proposing a RAD platform for EDA tools that enables the contributors to focus on the problem that they want to solve instead of “reinventing the wheel”. The proposed platform encompasses a user-friendly Tcl shell, a standardized data model, templates for quick creation of commands, a system-level Qt Graphical User Interface (GUI) and a user customizable Tk GUI, all synchronized by an event loop orchestrator with distributed processing capabilities. The amount of “boilerplate” code is reduced to a minimum in each stage of development. Finally, we propose the usage of a Continuous Integration/Continuous Deployment cycle to reduce the efforts on distribution of the tools developed on top of the platform. The platform was validated with the development of modules for the design flow of mixed-signal circuits.

The ring oscillator is the topology of choice in many modern applications given its simplicity, small area footprint, low-power and ability of being implemented with digital inverters. The oscillation frequency is dictated by the number of stages in the chain and the average delay of the inverters. In deep submicron processes, the very short propagation delay of logic gates makes the ring oscillator a very energy-efficient solution for high frequencies of operation, whereas for low frequencies the efficiency generally drops because larger capacitances must be driven to slow down the transitions. In this paper we propose a topology of oscillator that employs four injection-locked stacked ring oscillators, reusing current while the available supply potential is divided among these stages, naturally reducing the oscillation frequency while maintaining energy efficiency. The output signal is recovered to the supply rails through a level shifter circuit with feedback, allowing to adjust its threshold to deal with PVT variations. Simulation results show that the circuit operates from 3-10 MHz, while consuming 0.7 μW at 10 MHz, with a phase noise of -88.8 dBc/Hz at 100 kHz offset, leading to a FoM of -160 dB.

Injection locking of oscillators is a known technique to improve the oscillator's phase noise performance. Generally, this is done by running two or more oscillators that are linked through a passive or active coupling mechanism. Therefore, the power consumption (at least) doubles, leading to no improvement regarding the standard figure-of-merit (FoM). This work discloses a new coupling mechanism for locked oscillators, that reuses the supply current and builds upon the fact that inverters implemented in modern CMOS processes are able to reach reasonable oscillating frequencies even without using the full nominal supply voltage range. Instead of instantiating the oscillators “side-by-side”, the propo scheme stacks oscillators between the supply terminal, thus reusing the drawn current at the same time as dividing the available supply voltage among the oscillators. Aiming for proper voltage division, we exploit a property of the ring oscillators, in which they are able to keep the same power consumption while the number of phases is increased/decreased. In the presented approach, the phase-noise performance improves without a penalty in power consumption, thus also improving the FoM. Simulation results show that by coupling two oscillators at f0and 2f0, the higher frequency oscillator locks and inherits the better phase noise performance of the lower frequency oscillator, while reusing the same current, demonstrating the effectiveness of the proposed topology.

Discrete-time ΣΔ generally rely on switched-capacitor implementations that require operational amplifiers to implement the integrators. For ultra-deep submicron processes, the limited intrinsic gain of the transistor hinders the design of operational amplifiers. This paper proposes a topology for ΣΔ modulators that employs a low-power quasi-passive integrator. The input voltage is converted into the chargedomain by a transconductor-based front-end. The integration process is implemented with MOS capacitors instead of linear capacitors, which allows the reduction of charge leakage. While this design targets relatively low resolutions, due to the nonlinear nature of the passive integration, the absence of operational amplifiers enables the topology to fit in a very small area. The topology is validated by simulations with the design of a 1storder ΣΔ modulator. The circuit is designed in a 0.13 μm technology, fits in 40 × 60 μm2, performs at 100 MSps with 51.34 dB of SNDR and consumes 0.08 mW.

The vast majority of SAR ADCs on literature rely on very-linear capacitors to implement the DAC functionality. Still, if using the charge-sharing principle, a SAR ADC may employ MOS transistors used as capacitors (MOSCAPs) as DAC elements, benefiting from their higher capacitance density and broader availability. In this work, we exploit the body terminal of these MOSCAPs to adjust their capacitance and correct process mismatches. A background self-calibration scheme is presented and validated in a 12-bit 10 MSps SAR ADC. Post-layout simulations show that the algorithm is able to increase the effective-resolution of the ADC to 11.7 bits, in average. With a power consumption of 210 μW, the ADC achieves a figure of merit of 6.3 fJ/conversion-step. The presented ADC uses only 240 × 120 μm2of active area, including the calibration logic. Still, the deterministic calibration algorithm converges in less than 30k conversions. The achieved results make the proposed architecture very competitive for the range of moderate-resolution moderate-speed ADCs.

Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this paper, we propose a quaternary lookup table (LUT) structure, designed to replace or complement binary LUTs in field programmable gate arrays. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltagemode structures. A clock boosting technique is used to optimize the switches resistance and power consumption. The proposed implementation overcomes several limitations found in previous quaternary implementations published so far, such as the need for special features in the CMOS process or power-hungry current-mode cells. We present a full adder prototype based on the designed LUT, fabricated in a standard 130-nm CMOS technology, able to work at 100 MHz while consuming 122 μW. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design.

This paper reports a successive approximation register (SAR) analog-to-digital converter (ADC) based on the charge-sharing principle, which is known to be very energy efficient, but susceptible to the comparator offset. The ADC uses a new background calibration technique to cancel out the comparator mismatch and improve ADC linearity. Operation under low voltages is obtained through the use of voltage-boosted switches in the track-and-hold and the digitalto-analog converter. The techniques are demonstrated on a low-voltage low-power SAR ADC that operates from a minimum supply voltage of 350 up to 600 mV, suitable for circuits supplied by power harvesters. The prototype fabricated in a 130-nm CMOS process employs only regular-VTH transistors. It is able to convert at 3 MSps when supplied by 600 mV and at 200 kSps when supplied by 350 mV. At 350 mV, the measured effective-number-of-bits is 6.4, leading to a figure-of-merit of 5.04 fJ/conversion-step.

Radio frequency energy harvesting circuits have to harvest energy from very weak sources demanding high sensitivity and high efficiency. In this paper, an efficient RF energy harvester for wireless sensor networks is presented. The circuit is based on a multi-stage rectifier that exploit threshold self-compensation together with transistor gate and bulk stimulus. The input is matched to 50Ω through a matching network that provides voltage boosting to the rectifiers input terminal. According to the desired performance, a 910MHz harvester with matched input comprising a 10-Stage rectifier has been designed in an 130-nm CMOS process. Considering a -20dB input power signal the circuit can supply a 1MΩ load with 1V/1μW output voltage and power with an PCE of 10%. The circuit exhibits a maximum PCE of 27% at -16dBm with 0.8V/6.4μW output voltage and power. The achieved results exceed the performance of previous work in terms of energy efficiency at input power lower than -15dBm.

RC oscillators have lower cost and higher tuning range than LC oscillators. However, their phase noise performance is poor and in the case of the relaxation oscillator it is also far from the theoretical optimum. In this paper we present a new circuit of a quadrature relaxation oscillator with faster switching and high amplitude output signal to improve the FoM. The sizing of a prototype in a 130nm CMOS technology was done using a genetic algorithm tool. Simulation results show that the quadrature oscillator operating at 2.4 GHz achieves a figure of merit of -165 dBc/Hz.

The comparator-based asynchronous binary-search (CABS) analog-to-digital converter (ADC) topology is a good solution to achieve high conversion rate at low power dissipation. In this paper we present an architecture of CABS ADC with a background calibration scheme, that allows the use of smaller devices, further reducing the power consumption. Unlike the foreground calibration, it does not require the ADC precalibration before it starts to operate, reducing the system-level complexity. The calibration is performed through the use of a digital-to-analog converter (DAC) serving as reference for the self-calibrated comparators. We also propose threshold reconfigurable comparators, reducing the number of the devices used. In this paper, we design a 7-bit 2-step ADC comprehending a 2-bit successive approximation register (SAR) ADC for the front-end and the proposed 5-bit CABS ADC for the back-end. Monte-Carlo simulations for the 2-step design show that, sampling at 250MSps, the ADC has 450μW of power consumption with a 6.92 effective number of bits resulting in a figure of merit of 14.86fJ/conversion step.

A wide range of applications, including wireless sensor networks (WSN) and biomedical, motivate the design of energy-efficient analog-to-digital converters (ADCs). We propose and discuss the design of an ultra-low power charge-sharing successive approximation ADC. The proposed ADC employs an internal step-down voltage regulator to reduce the energy spent on the digital-to-analog converter (DAC), and we demonstrate that this approach leads to a 5× reduction in the DAC power consumption. Moreover, a self-calibration technique is implemented in order to mitigate the impact of process variations on the ADC linearity. Simulation results show that the proposed 10-bit ADC, designed in a 90 nm technology, consumes 1.79 μW from a 1V supply, while sampling at 1 MSps and providing 9.34 effective bits (mean values based on Monte-Carlo simulation). The achieved figure-of-merit (FOM) of 2.87 fJ/conversion step (mean value) places this ADC among the state-of-the-art designs in low-speed moderate-resolution ADCs.

Modern RF communication technologies often shift the baseband processing to the digital domain, thus requiring an analog-to-digital converter (ADC) as interfacing element. For most applications, those ADCs must provide very-high conversion rate at low cost (effective in terms of area and power). We propose an improved binary-search ADC topology, which relies on a pipeline of threshold-reconfigurable comparators and a time-interleaved track-and-hold arrangement. We also propose a topology of threshold-reconfigurable comparator and a corresponding effective design methodology based on optimization through genetic algorithms. In this paper, we design a proof-of-concept 5-bit ADC which does not require calibration as most similar designs. Monte Carlo simulations for the proposed design show that, sampling at 1.5 GSps, the ADC consumes 5 mW providing 4.6 effective bits and a figure of merit of 138 fJ/conversion step (mean values).

This paper describes the implementation of an IR-UWB transmitter using an oscillator, and where the pulse duration is controlled digitally by the oscillator frequency. In this new topology, the consumption is reduced to the leakage current when it is not producing a pulse, ensuring high power efficiency even for low data rates. The proposed circuit is inductorless and implemented in a standard UMC 130nm CMOS technology to be die area efficient and low cost. The design and simulation results are presented, including pads and off-chip elements as bonding wires and antenna models. The transmitter die area with pads is 0.0783 mm2, and the energy consumption per pulse is 25.5 pJ from a 1.2 V supply.

Analog designers are challenged by increasingly complex device models and lowered signal swing as the CMOS processes scale. At the same time, new trends and emerging technologies pose tighter design constraints. However, the cheap computational resources nowadays enable the use of the mature electrical simulators and device models in simulation-in-a-loop optimization techniques. In this work, we present a flexible circuit optimization tool for analog designs which relies on evolutionary algorithms. Moreover, we employ logistic functions to determine the fittest individuals. The benchmarking test shows that the program is able to dimension an operational transconductance amplifier (OTA) based on the topology netlist in less than 15 minutes, without resorting to any knowledge base, initial guess or simplified models. The achieved performance suggests that the tool may be integrated in an existing design flow with huge benefits.

Current trends constantly increase the need for ultra-low power solutions for the embedded and portable hard ware. One circuit component required in wide range of devices is the analog-to-digital converter (ADC). In this paper we propose an extremely energy-efficient successive approximation register (SAR) ADC, in which we have overcome the limitations of conventional approaches through topological improvements. Further, advances include a novel bootstrapped track and hold (T/H) circuitry. Statistical simulations indicate an ADC with a figure of merit (FOM) of 11.9 fJ per conversion step, and an effective number of bits (ENOB) of 9.2, operating close to Nyquist frequency, sampling at 1 Msps. To put it into perspective, consuming only 7 pJ/sample, this ADC is able to work at its maximum speed for more than 40 years with the total energy of a single alkaline AA battery.