Timing recovery for an ATM network is inherently different from its circuit-switched counterpart. There are two generic approaches to ATM timing recovery, namely, non-synchronous methods which rely on cell jitter filtering and synchronous methods which use a common reference clock. The latter approach has better jitter/wander performance. This is particularly significant for circuit emulation of existing hierarchical signals (e.g. DSn signals), which have stringent jitter/wander requirements. This paper compares several methods for timing recovery in a synchronous network environment and discusses the fundamental concept, implementation, and performance of three synchronous techniques: synchronous frequency encoding technique (SFET), time stamp (TS), and synchronous residual time stamp (SRTS). Among these methods, it is concluded that the SRTS method, invented by the authors, is the most efficient. SRTS has been accepted by ITU-T as the timing recovery standard for AAL-1 (ATM Adaptation Layer-Circuit Emulation). Practical implementation considerations of the SRTS technique and its robustness against cell loss are also examined in this paper. In addition, it is shown that a strong analogy can be drawn between SRTS and conventional pulse stuffing synchronization techniques so that the jitter performance for SRTS is comparable to that of the circuit-switched network.>

The source coding scheme for the experimental research prototype that is currently being designed to demonstrate the digital coding of high-definition television (HDTV) for transport within the proposed broadband integrated services digital network (ISDN) fiber optic network is described. The network interface will be used on a packet-based asynchronous transfer mode (ATM) technology. To maximize coding efficiency, run-length coding and variable word length coding are also incorporated in the system. The scheme uses multiple block-size Hadamard transform coding that can be implemented using a set of two-tap filters in a simple subband structure. In spite of the low hardware complexity, which is of dominant importance in the overall system performance, high coding efficiency is obtained. The major features and advantages of this scheme are outlined.>

The design of active amplitude and delay equalizers to be used in private line data systems is considered. These equalizers provide sufficient flexibility of adjustment so that one type of amplitude equalizer and one type of delay equalizer are sufficient for all applications. They replace families of passive equalizers which permitted relatively limited or no adjustment.