Demo Data from EDBT 2026 / reviewers in the wild / expert
Szu-Chi Chung
dblp:118/3377
· DBLP profile ↗
6ranked-venue papers
3as first author
2since 2021 · last 2024
0000-0002-3137-6188ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorSecurity and privacy · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Interdisciplinary, comprehensive, and emerging computing
1 paper |
Bioinformatics and computational biology · 100% | |
| Network and information security
1 paper |
Hardware security and side channels · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Bioinformatics and computational biology
minimum energy path |
0.8 | 1 | 2024 | CLEAPA: a framework for exploring the conformational landscape of cryo-EM using energy-aware pathfinding algorithm · Bioinform. 2024 |
Bioinformatics and computational biology
molecular conformation |
0.2 | 1 | 2024 | CLEAPA: a framework for exploring the conformational landscape of cryo-EM using energy-aware pathfinding algorithm · Bioinform. 2024 |
Bioinformatics and computational biology
structural biology |
0.2 | 1 | 2024 | CLEAPA: a framework for exploring the conformational landscape of cryo-EM using energy-aware pathfinding algorithm · Bioinform. 2024 |
Hardware security and side channels › side-channel countermeasures
power analysis countermeasure |
0.1 | 1 | 2012 | An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor · CHES 2012 |
Hardware security and side channels
side-channel countermeasures |
0.1 | 1 | 2012 | An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor · CHES 2012 |
Hardware accelerators and domain-specific architectures
cryptographic accelerator |
0.0 | 1 | 2012 | An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor · CHES 2012 |
Hardware accelerators and domain-specific architectures › cryptographic accelerator
elliptic curve processor |
0.0 | 1 | 2012 | An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor · CHES 2012 |
Methods — techniques the papers use, named apart from their topics
latent space reconstruction · 0.8graph search · 0.8energy-aware pathfinding · 0.8randomization · 0.3montgomery multiplication · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | CLEAPA: a framework for exploring the conformational landscape of cryo-EM using energy-aware pathfinding algorithmabstractMOTIVATION: Cryo-electron microscopy (cryo-EM) is a powerful technique for studying macromolecules and holds the potential for identifying kinetically preferred transition sequences between conformational states. Typically, these sequences are explored within two-dimensional energy landscapes. However, due to the complexity of biomolecules, representing conformational changes in two dimensions can be challenging. Recent advancements in reconstruction models have successfully extracted structural heterogeneity from cryo-EM images using higher-dimension latent space. Nonetheless, creating high-dimensional conformational landscapes in the latent space and then searching for preferred paths continues to be a formidable task. RESULTS: This study introduces an innovative framework for identifying preferred trajectories within high-dimensional conformational landscapes. Our method encompasses the search for the minimum energy path in the graph, where edge weights are determined based on the energy estimation at each node using local density. The effectiveness of this approach is demonstrated by identifying accurate transition states in both synthetic and real-world datasets featuring continuous conformational changes. AVAILABILITY AND IMPLEMENTATION: The CLEAPA package is available at https://github.com/tengyulin/energy_aware_pathfinding/. Teng-Yu Lin, Szu-Chi Chung |
Bioinform. | 2 |
| 2021 | Cryo-Ralib - A Modular Library for Accelerating Alignment in CRYO-EMabstractThanks to GPU-accelerated processing, cryo-EM has become a rapid structure determination method that permits capture of dynamical structures of molecules in solution, which has been recently demonstrated by the determination of COVID-19 spike protein in March, shortly after its breakout in late January 2020. This rapidity is critical for vaccine development in response to the emerging pandemic. Compared to the Bayesian-based 2D classification widely used in the work-flow, the multi-reference alignment (MRA) is less popular. It is time-consuming despite its superior in differentiating structural variations. Interestingly, the Bayesian approach has higher complexity than MRA. We thereby reason that the popularity of Bayesian is gained through GPU acceleration, where a modular acceleration library for MRA is lacking. Here, we introduce a library called Cryo-RALib that expands the functionality of CUDA library used by GPU ISAC. It contains a GPU-accelerated MRA routine for accelerating MRA-based classification algorithms. In addition, we connect the cryo-EM image analysis with the python data science stack to make it easier for users to perform data analysis and visualization. Benchmarking on the TaiWan Computing Cloud (TWCC) shows that our implementation can accelerate the computation by one order of magnitude. The library is available at https://github.com/phonchi/Cryo-RAlib. Szu-Chi Chung, Cheng-Yu Hung, Huei-Lun Siao, Hung-Yi Wu, Wei-Hau Chang, I-Ping Tu |
ICIP | 1 |
| 2015 | Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic ThreeabstractTo support emerging pairing-based protocols related to cloud computing, an efficient algorithm/hardware codesign methodology of ηT pairing over characteristic three is presented. By mathematical manipulation and hardware scheduling, a single Miller's loop can be executed within 17 clock cycles. Furthermore, we employ torus representation and exploit the Frobenius map to lower the computation cost of final exponentiation. Pipelining and parallelization datapath are also exploited to shorten the critical path delay. Finally, by choosing suitable multiplier architecture and selecting an appropriate number of multipliers, Miller's loop and final exponentiation can be computed in a fully pipelined manner. With these schemes, a test chip for the proposed pairing accelerator has been fabricated in 90-nm CMOS 1P9M technology with a core area of 1.52 × 0.97 mm2. It performs a bilinear pairing computation over F(397) in 4.76 μs under 1.0 V supply and achieves 178% improvement to relative works in terms of area-time (AT) product. To support higher level of security, a 126-bit secure pairing accelerator that can complete a bilinear pairing computation over F(3709) in 36.2 μs is implemented and this result is at least 31% better than relative works in terms of AT product. Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee |
IEEE Trans. Very Large Scale Integr. Syst. | 1 |
| 2014 | Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element ArchitectureabstractElliptic curve cryptography (ECC) for portable applications is in high demand to ensure secure information exchange over wireless channels. Because of the high computational complexity of ECC functions, dedicated hardware architecture is essential to provide sufficient ECC performance. Besides, crypto-ICs are vulnerable to side-channel information leakage because the private key can be revealed via power-analysis attacks. In this paper, a new heterogeneous dual-processing-element (dual-PE) architecture and a priority-oriented scheduling of right-to-left double-and-add-always EC scalar multiplication (ECSM) with randomized processing technique are proposed to achieve a power-analysis-resistant dual-field ECC (DF-ECC) processor. For this dual-PE design, a memory hierarchy with local memory synchronization scheme is also exploited to improve data bandwidth. Fabricated in a 90-nm CMOS technology, a 0.4- mm2160-b DF-ECC chip can achieve 0.34/0.29 ms 11.7/9.3 μJ for one GF(p)/GF(2m) ECSM. Compared to other related works, our approach is advantageous not only in hardware efficiency but also in protection against power-analysis attacks. Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee |
IEEE Trans. Very Large Scale Integr. Syst. | 2 |
| 2012 | An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee |
CHES | 2 |
| 2012 | A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistanceabstractIn order to support high speed application such as cloud computing, we propose a new elliptic curve cryptographic (ECC) processor architecture. The proposed processor includes a 3 pipelined-stage full-word Montgomery multiplier which requires much fewer execution cycles than that of previous methods. To reach real-time requirement, the time-cost pre-computation steps of Montgomery modular multiplication are achieved by hardware as well. Moreover, our proposed processor is resistant to the simple power analysis (SPA) attack by using the Montgomery ladder-based elliptic curve scalar multiplication (ECSM). Even the Montgomery ladder method inherently has operation overhead compared with traditional binary ECSM, both of hardware sharing and parallelization techniques are exploited to improve the hardware performance. Synthesized in TSMC 90nm CMOS technology, our proposed ECC processor performs a 256-bit ECSM in 120µs over prime field with 540K gate counts. This result is at least 25% better than relative works in terms of area-time (AT) product. Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee |
ISCAS | 1 |