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Wen-Chieh Chen

dblp:118/4827 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%
Computer graphics and multimedia
1 paper
Image and video processing · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
image processing accelerator
0.212014
A New Hardware-Efficient Algorithm and Reconfigurable Architecture for Image Contrast Enhancement · IEEE Trans. Image Process. 2014
Image and video processing › image enhancement
contrast enhancement
0.112014
A New Hardware-Efficient Algorithm and Reconfigurable Architecture for Image Contrast Enhancement · IEEE Trans. Image Process. 2014
Image and video processing
image enhancement
0.112014
A New Hardware-Efficient Algorithm and Reconfigurable Architecture for Image Contrast Enhancement · IEEE Trans. Image Process. 2014

Methods — techniques the papers use, named apart from their topics

reconfigurable architecture · 0.4gamma correction · 0.4approximation · 0.4
YearPublicationVenuePosition
2014 A New Hardware-Efficient Algorithm and Reconfigurable Architecture for Image Contrast Enhancement
abstract
Contrast enhancement is crucial when generating high quality images for image processing applications, such as digital image or video photography, liquid crystal display processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a novel hardware-oriented contrast enhancement algorithm which can be implemented effectively for hardware design. In order to be considered for hardware implementation, approximation techniques are proposed to reduce these complex computations during performance of the contrast enhancement algorithm. The proposed hardware-oriented contrast enhancement algorithm achieves good image quality by measuring the results of qualitative and quantitative analyzes. To decrease hardware cost and improve hardware utilization for real-time performance, a reduction in circuit area is proposed through use of parameter-controlled reconfigurable architecture. The experiment results show that the proposed hardware-oriented contrast enhancement algorithm can provide an average frame rate of 48.23 frames/s at high definition resolution 1920 × 1080.
Shih-Chia Huang, Wen-Chieh Chen
IEEE Trans. Image Process.2