Mingzhe Zhang 0002

dblp:118/5481-2 · DBLP profile ↗
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4ranked-venue papers
1as first author
4since 2021 · last 2025
0009-0007-1464-5271ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author · 4 since 2021
YearPublicationVenuePosition
2025 Productively Generating a High-Performance Linear Algebra Library on FPGAs
abstract
Linear algebra computations can be greatly accelerated using spatial accelerators on FPGAs. As a standard building block of linear algebra applications, BLAS covers a wide range of compute patterns that vary vastly in data reuse, bottleneck resources, matrix storage layouts, and data types. However, existing implementations of BLAS routines on FPGAs are stuck in the dilemma of productivity and performance. They either require extensive human effort or fail to leverage the properties of routines for acceleration. We introduce Lasa, a framework composed of a programming model and a compiler, designed to address the dilemma by abstracting (for productivity) and specializing (for performance) the architecture of a spatial accelerator. The programming model realizes systolic arrays using uniform recurrence equations and space-time transforms. Streaming tensors, an intuitive dataflow-style abstraction, is proposed to uniformly describe the movement, storage, and transpose of input and output data across the spatial components. According to streaming tensors, a customized memory hierarchy is automatically built on an FPGA by our compiler. The compiler further specializes the architecture with transparent optimizations on FPGAs. Using this framework, we develop a complete BLAS library, demonstrating performance in parity with expert-written HLS code for BLAS level 3 routines, 76%–94% machine peak for level 1 and 2 routines, and 1.6X–13X speedup by leveraging the matrix properties such as symmetry, triangularity, and bandness.
Xiaochen Hao, Mingzhe Zhang 0002, Ce Sun 0001, Zhuofu Tao, Hongbo Rong, Yu Zhang 0086, Lei He 0001, Eric Petit 0002, Yun Liang 0001
ACM Trans. Reconfigurable Technol. Syst.2
2024 POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations
abstract
This paper aims at high and portable performance for tensor computations across spatial (e.g., FPGAs) and vector architectures (e.g., GPUs). The state-of-the-art usually address performance portability across vector architectures (CPUs and GPUs). However, they either miss FPGAs or do not achieve high performance. Without a common architectural abstraction, they program and optimize spatial and vector devices separately, causing low portability.
Xiaochen Hao, Hongbo Rong, Mingzhe Zhang 0002, Ce Sun 0001, Hong H. Jiang, Yun Liang 0001
FPGA3
2024 MatFactory: A Framework for High-Performance Matrix Factorization on FPGAs
abstract
Matrix factorization is a widely used powerful tool in signal processing, machine learning and high performance computing. For accelerating matrix factorization, FPGAs are suitable platforms, as they can build wide and deep pipelines with favorable power efficiency. Factorizing matrices on FPGAs is thus desirable; however, there is no infrastructure on FPGAs for matrix factorization so far, as it involves several challenges: applicability and scalability of the circuit, pipelining of irregular computing patterns, and effective data caching given the limited memory bandwidth.
Mingzhe Zhang 0002, Xiaochen Hao, Hongbo Rong
ICCAD1
2023 Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs
abstract
Linear algebra can often be significantly expedited by spatial accelerators on FPGAs. As a broadly-adopted linear algebra library, BLAS requires extensive optimizations for routines that vary vastly in data reuse, bottleneck resources, matrix storage layouts, and data types. Existing solutions are stuck in the dilemma of productivity and performance. We introduce Lasa, a framework composed of a programming model and a compiler, that addresses the dilemma by abstracting (for productivity) and specializing (for performance) the architecture of a spatial accelerator. Lasa abstracts a compute and its I/O as two dataflow graphs. A compiler maps the graphs onto systolic arrays and a customized memory heirarchy. The compiler further specializes the architecture transparently. In this framework, we develop 14 key BLAS routines, and demonstrate performance in parity with expert-written HLS code for BLAS level 3 routines, >=80% machine peak performance for level 2 and 1 routines, and 1.6X-7X speed up by taking advantage of matrix properties of symmetry, triangularity and bandness.
Xiaochen Hao, Mingzhe Zhang 0002, Ce Sun 0001, Zhuofu Tao, Hongbo Rong, Yu Zhang 0086, Lei He 0001, Eric Petit 0002, Yun Liang 0001
FCCM2