EDBT 2026 Demo / reviewers in the wild / expert
Xiongren Xiao
dblp:118/5580
· DBLP profile ↗
11ranked-venue papers
0as first author
7since 2021 · last 2025
0000-0002-3596-071XORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 8 · 5 since 2021Security and privacy · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Fast Game Verification for Safety- and Security-Critical Distributed ApplicationsabstractThe co-verification of safety and security is a necessary process for safety- and security-critical distributed applications, but conflicts exist between safety and security. The state-of-the-art Block-based Vulnerability Pre-assignment (BVP) and Reversed Block-based Time Pre-assignment (RBTP) co-verification techniques of safety and security have three main limitations: 1) only co-verifying the boundary values and ignoring the verification of non-boundary values; 2) algorithm redundancy (i.e., BVP and RBTP must be used simultaneously) makes the verification process complex and cumbersome; and 3) only one safety attribute and one security attribute participate in the co-verification. In this study, we explore the causal mechanisms for the mutual influence between safety and security: 1) they compete with each other in relation to Worst Case Execution Time (WCET); 2) there is a lack of cooperation between the two; and 3) both are pursuing maximum performance for each individual. Above causal mechanisms precisely conforms to the problem of maximizing benefits in non-cooperative games (i.e., Nash equilibrium). Therefore, we propose the Fast Game Verification (FGV) based on non-cooperative game to co-verify reliability in safety and confidentiality in security. FGV achieves non-boundary value co-verification and avoids redundancy. We develop Fast Game Verification plus plus (FGV++) algorithm to co-verify multiple safety attributes and multiple security attributes. We conduct actual cases of distributed applications. In terms of the co-verification of two attributes, FGV demonstrates average acceptance rate of 59.96% within 0.638 s, surpassing both BVP&RBTP by 6.94% (within 0.812 s); FGV++ achieves average acceptance rate of 58.73% within 0.663 s, exhibiting a 4.53% advantage over BVP and RBTP. In the co-verification of four attributes, the average acceptance rate of FGV++ has increased to 61.07% within 1.34102 s. Guoqi Xie, Xiongren Xiao, Renfa Li |
IEEE Trans. Dependable Secur. Comput. | 4 |
| 2024 | Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive NetworkingabstractTime-Sensitive Networking (TSN) realizes high bandwidth and time determinism for data transmission and thus becomes the crucial communication technology in time-critical systems. The Gate Control List (GCL) is used to control the transmission of different classes of traffic in TSN, including Time-Triggered (TT) flows, Audio-Video-Bridging (AVB) flows, and Best-Effort (BE) flows. Most studies focus on optimizing GCL synthesis by reserving the preceding time slots to serve TT flows with the strict delay requirement, but ignore the deadlines of non-TT flows and cause the large delay. Therefore, this paper proposes a comprehensive scheduling method to enhance the real-time scheduling of AVB flows while guaranteeing the time determinism of TT flows. This method first optimizes GCL synthesis to reserve the preceding time slots for AVB flows, and then introduces the Earliest Deadline First (EDF) method to further improve the transmission of AVB flows by considering their deadlines. Moreover, the worst-case delay (WCD) analysis method is proposed to verify the effectiveness of the proposed method. Experimental results show that the proposed method improves the transmission of AVB flows compared to the state-of-the-art methods. Libing Deng, Ryo Kurachi, Hiroaki Takada, Xiongren Xiao, Renfa Li, Guoqi Xie |
ACM Trans. Design Autom. Electr. Syst. | 5 |
| 2023 | Cyber-Physical Systems Design in An Uncertain Environment with Time Uncertainty ConcernabstractMultiple processors system on chip (MPSoC) has been the trend in cyber-physical systems (CPSs), and reasonable partitioning for MPSoC resources is a critical step in CPSs design. The uncertainties of environment and time are both important factors that need to be considered in the design, but none of the previous work pays attention to two uncertainties at the same time. The state-of-the-art work presented a detailed process of applying uncertain programming to solve the partitioning problem, which provides a solution for designing in an uncertain environment. However, this work only considers the bipartition scenario which cannot be directly applied to MPSoC, and it does not focus specifically on time uncertainty. In this paper, we propose a method for modeling the MPSoC partitioning problem in an uncertain environment, with the time uncertainty concern. We present the uncertain model that can be applied to the multiple optional resources scenario. We build the optimization model with the objective of minimizing time, analyze two different cases of minimizing the uncertain time, and finally prove a unified deterministic model to solve. We come up with three algorithms, including the heuristic algorithm, the genetic algorithm, and the exact algorithm, and experiments show that the heuristic algorithm and the genetic algorithm can obtain good approximate solutions compared with the exact algorithm. Lida Huang, Xiongren Xiao, Yan Liu 0032, Guoqi Xie, Renfa Li |
ICPADS | 3 |
| 2023 | RTISM: Real-Time Inter-VM Communication Based on Shared Memory for Mixed-Criticality FlowsabstractVirtual machines (VMs) have been increasingly deployed in real-time systems to enhance heterogeneous resource sharing. Despite being isolated for security and prevention of failure propagation, VMs need to communicate with each other to complete certain tasks jointly. A real-time inter-VM communication framework has been proposed based on VirtIO, which is in essence a mechanism of message passing with high latency and low scalability on data amount. In contrary, IVSHMEM implements inter-VM communication with shared memory, which is generally fast and large in throughput. Unfortunately, IVSHMEM does not resolve resource contention between flows and hence cannot be applied in real-time scenarios. In this work, we propose a real-time inter-VM communication framework RTISM built upon shared memory and IVSHMEM. RTISM provides priority-based scheduling and supports mixed-criticality flows. Worst-Case Response Time (WCRT) analysis is reported to bound the end-to-end communication delay and a Limited Priority Assignment (LPA) algorithm is developed to enhance schedulability. Experimental evaluation shows that (i) RTISM has about 4 times higher throughput than the VirtIO-based inter-VM communication framework; (ii) LPA improves schedulability by over 25% compared to the state-of-the-art; (iii) WCRT produces a tight bound. Zonghong Li, Guoqi Xie, Wenhong Ma, Xiongren Xiao, Yong Xie 0003, Wei Ren 0002, Wanli Chang 0001 |
RTSS | 4 |
| 2022 | A low-delay AVB flow scheduling method occupying the guard band in Time-Sensitive Networking
Libing Deng, Xiongren Xiao, Hong Liu 0006, Renfa Li, Guoqi Xie |
J. Syst. Archit. | 2 |
| 2022 | A Survey of Low-Energy Parallel Scheduling AlgorithmsabstractHigh energy consumption is one of the biggest obstacles to the rapid development of computing systems, and reducing energy consumption is quite urgent and necessary for sustainable computing. Low-energy scheduling based on dynamic voltage and frequency scaling (DVFS) is one of the most commonly used energy optimization techniques. Recent survey works have reviewed some low-energy scheduling algorithms, but there is currently no systematic review in low-energyparallelscheduling algorithms. With the increasing complexity of function requirements, many parallel applications have been executed in various sustainable computing systems. In this paper, we survey recent advances in low-energy parallel scheduling algorithms according to three scheduling styles, namely: 1) energy-efficient parallel scheduling algorithms; 2) energy-aware parallel scheduling algorithms; and 3) energy-conscious parallel scheduling algorithms. Low-energy parallel scheduling algorithms basically involve five categories of 1) heuristic algorithms; 2) meta-heuristic algorithms; 3) integer programming algorithms; 4) machine learning algorithms; and 5) game theory algorithms. Further, we introduce the future trends in low-energy parallel scheduling algorithms from the perspectives of new requirements and future developments. By surveying the recent advances and introducing the future trends, we expect to provide researchers with a systematic reference and development directions in low-energy parallel scheduling for sustainable computing systems. Guoqi Xie, Xiongren Xiao, Renfa Li, Keqin Li 0001 |
IEEE Trans. Sustain. Comput. | 2 |
| 2021 | Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded DevicesabstractWith Internet of things technologies, billions of embedded devices, including smart gateways, smart phones, and mobile robots, are connected and deeply integrated. Almost all these embedded devices are battery-constrained and energy-limited systems. In recent years, several works used energy pre-assignment techniques to study the dynamic energy-constrained scheduling of a parallel application in heterogeneous multicore embedded systems. However, the existing energy pre-assignment techniques cannot satisfy the actual energy constraint, because it is the joint constraint on dynamic energy and static energy. Further, the modeling and verification of these works are based on the simulations, which have not been verified in real embedded devices. This study aims to propose a dynamic and static energy-constrained scheduling framework in heterogeneous multicore embedded devices. Solving this problem can utilize existing energy pre-assignment techniques, but it requires a deeply integrated design flow and methodology. The design flow consists of four processes: (1) power and energy modeling; (2) power parameter measurement; (3) basic framework design including energy pre-assignment; and (4) framework optimization. Each design flow has corresponding design methodology. Both our theoretical analysis and practical verification using the low-power ODROID-XU4 device confirm the effectiveness of the proposed framework. Guoqi Xie, Xiongren Xiao, Renfa Li |
ACM Trans. Design Autom. Electr. Syst. | 3 |
| 2018 | Energy-Efficient Fault-Tolerant Scheduling of Reliable Parallel Applications on Heterogeneous Distributed Embedded SystemsabstractDynamic voltage and frequency scaling (DVFS) is a well-known energy consumption optimization technique in embedded systems and dynamically scaling down the voltage of a chip has been developed to achieve energy-efficient optimization. However, this operation may lead to a sharp rise in transient failures of processors and consequently weaken the reliability of systems. Reliability goal is an important functional safety requirement and must be satisfied for safety-critical applications. In this study, we aim to implement energy-efficient fault-tolerant scheduling for a reliable parallel application on heterogeneous distributed embedded systems, where the parallel application is described by a directed acyclic graph (DAG). An energy-efficient scheduling with a reliability goal (ESRG) algorithm is presented to reduce the energy consumption while satisfying the reliability goal for the parallel application. Considering that the application's reliability goal is unreachable if its reliability goal exceeds a certain threshold via ESRG, we further propose an energy-efficient fault-tolerant scheduling with a reliability goal (EFSRG) algorithm to reduce the energy consumption while satisfying the reliability goal based on an active replication scheme. Experimental results confirm that the energy consumption reduced by the proposed EFSRG algorithm is higher than those reduced by other approaches under different scale conditions. Guoqi Xie, Yuekun Chen, Xiongren Xiao, Cheng Xu 0001, Renfa Li, Keqin Li 0001 |
IEEE Trans. Sustain. Comput. | 3 |
| 2017 | Schedule length minimization of parallel applications with energy consumption constraints using heuristics on heterogeneous distributed systemsabstractSummary Energy consumption is one of the primary design constraints in heterogeneous parallel and distributed systems ranging from small embedded devices to large‐scale data centers. The problem of minimizing the schedule length of an energy consumption‐constrained parallel application has been studied recently in homogeneous systems with a shared memory. To adopt the heterogeneity and distribution of high‐performance computing systems, this study solves the problem of minimizing the schedule length of an energy consumption‐constrained parallel application in heterogeneous distributed systems based on a dynamic voltage and frequency scaling energy‐efficient design technique. The aforementioned problem is divided into 2 subproblems in this study, namely, satisfying energy consumption constraint and minimizing schedule length. The first subproblem is solved by transferring the energy consumption constraint of the application to that of each task, whereas the second subproblem is solved by heuristically scheduling each task with low time complexity. Experiments using both fast Fourier transform and Gaussian elimination parallel applications show that the actual energy consumption values do not always exceed but are close to the given energy consumption constraints. In addition, the minimum schedule lengths are generated using the proposed algorithm. Guoqi Xie, Xiongren Xiao, Renfa Li, Keqin Li 0001 |
Concurr. Comput. Pract. Exp. | 2 |
| 2017 | Energy-Efficient Scheduling Algorithms for Real-Time Parallel Applications on Heterogeneous Distributed Embedded SystemsabstractEnergy consumption minimization is one of the primary design requirements for heterogeneous distributed systems. State-of-the-art algorithms are used to study the problem of minimizing the energy consumption of a real-time parallel application with precedence constrained tasks on a heterogeneous distributed system by introducing the concept of latest finish time (LFT) to reclaim the slack time based on the dynamic voltage and frequency scaling (DVFS) energy-efficient design optimization technique. However, the use of DVFS technique alone is insufficient, and the energy consumption reduction is limited because scaling down the frequency is restricted in practice. Furthermore, these studies merely minimize energy consumption through a local energy-efficient scheduling algorithm, such as reducing the energy consumption for each task on the fixed processor, rather than a global energy-efficient scheduling algorithm, such as reducing the energy consumption for each task on different processors. This study solves the problem of minimizing the energy consumption of a real-time parallel application on heterogeneous distributed systems by using the combined non-DVFS and global DVFS-enabled energy-efficient scheduling algorithms. The non-DVFS energy-efficient scheduling (NDES) algorithm is solved by introducing the concept of deadline slacks to reduce the energy consumption while satisfying the deadline constraint. The global DVFS-enabled energy-efficient scheduling (GDES) algorithm is presented by moving the tasks to the processor slacks that generate minimum dynamic energy consumptions. Results of the experiments show that the combined NDES&GDES algorithm can save up to 36.25-55.65 percent of energy compared with state-of-the-art counterparts under different scales, parallelism, and heterogeneity degrees of parallel applications. Guoqi Xie, Xiongren Xiao, Renfa Li, Keqin Li 0001 |
IEEE Trans. Parallel Distributed Syst. | 3 |
| 2014 | A High-Performance DAG Task Scheduling Algorithm for Heterogeneous Networked Embedded SystemsabstractA high-performance scheduling for a DAG (Directed Acyclic Graph) task graph on heterogeneous networked embedded systems or parallel and distributed systems is to maximize concurrency and minimize inter-processor communication. Most of the algorithms using upward rank value for task prioritizing and earliest finish time for processor assignment. But both approaches ignored the heterogeneity of system and could not create accurate and efficient schedules. Yet no one has doubled about and recognized that. A fully heterogeneous task scheduling algorithm is proposed to address the above problems in this paper. The fundamentals of DAG model and corresponding algorithms are investigated. New concepts called Heterogeneous Upward Rank Value (HURV) and Heterogeneous Priority Rank Value (HPRV) are defined. An algorithm called Heterogeneous Select Value (HSV) is proposed in paper. Both benchmark and extensive experimental evaluation demonstrate the significant improvements in proposed algorithm. Guoqi Xie, Renfa Li, Xiongren Xiao, Yuekun Chen |
AINA | 3 |