The frequency of a digital phaselock loop (DPLL) is necessarily quantized. Feedback around the quantizing nonlinearity leads to a steady-state limit cycle. Properties of the limit cycle were obtained by computer simulation, and are reported here. Empirical formulas for guidance in DPLL design were developed.

For pt.I, see ibid., vol.41, no.3, p.502-208 (1993). Properties of a specific class of interpolators that are based upon polynomials are discussed. Several implementations are described, one of which is particularly convenient in practical hardware. Simulations demonstrate that simple interpolators give excellent performance. In many cases, two-point, linear interpolation is adequate. If better performance is needed, classical four-point, third-order polynomials could be used. Better yet, a novel four-point interpolating filter with piecewise-parabolic impulse response can have performance superior to that of the standard cubic interpolator and still be implemented much more simply. The NCO-based control method presented in Part I is shown to be equivalent to a conventional phase locked loop and its operation is verified by simulation.>

Timing adjustment in a digital modem must be performed by interpolation if sampling is not synchronized to the data symbols. The author describes the fundamental equation for interpolation, proposes a method for control, and outlines the signal-processing characteristics appropriate to an interpolator. A review of previous results and a tutorial exposition of the subject are given, along with new results.>

A simple algorithm for detection of timing error of a synchronous, band-limited, BPSK or QPSK data stream is proposed. The algorithm requires only two samples per symbol for its operation. One of the two samples is also used for the symbol decision. Derivation of thescurve reveals a sinusoidal shape.

One method of simulating an analog filter on a digital computer is to transform the continuous-time differential equation of the filter into a corresponding discrete-time difference equation. This paper describes the useful properties of the step-invariant transformation.

Among other applications, frequency-tracking loops are employed in digital-data receivers, either as a frequency-acquisition aid for phase-locked coherent reception, or as the sole carrier-frequency control for noncoherent reception. This article provides details of design and performance of the frequency-difference detector that lies at the heart of the loop.

The role of phase equivocation in hangup of phase-lock loops is clarified. Equivocation can occur and lead to hangup if and only if the phase detector characteristic is discontinuous at the reverse-slope null.

Phase-lock loops using charge pumps are found to have remarkably good potential for accurate phase tracking. The several favorable factors are described and numerical calculations provide examples of typical errors. Inaccuracy as small as fractional microcycles appears to be an attainable goal.

Synchronization of narrow-band data signals is plagued by self-noise arising from the randomness of the data stream. The disturbance can be resolved into in-phase and quadrature components with respect to the recovered carrier or clock. Only the quadrature component necessarily contributes to phase jitter of the recovered reference. Spectrum of the quadrature component, in many cases, vanishes at the reference frequency. Circuit precautions are needed to avoid cross coupling the in-phase disturbance into phase jitter.

Phase/frequency detectors deliver output in the form of three-state, digital logic. Charge pumps are utilized to convert the timed logic levels into analog quantities for controlling the locked oscillators. This paper analyzes typical charge-pump circuits, identifies salient features, and provides equations and graphs for the design engineer.

Synchronization is a fundamental problem in digital cornmunications systems. In radar, sonar, and navigation systems, synchronization is connected with the objectives of measuring range, velocity, and position. This Special Issue is devoted specifically to the synchronization problem as it relates to digital communications engineering and technology. In the implementation of digital communication systems, one must distinguish among several types of synchronization. Some of these are: 1 ) carrier synchronization, 2) clock synchronization. 3) codeword and node synchronization, 4) frame synchronization, and 5) network synchronization. This Special Issue provides papers which address each of the above synchronization types. Additionally, special problems related to the operation and performance of synchronizers which employ the phase-lock principle are provided. A brief overview of the content of this Special Issue is presented.

Methods are presented for determining the modulation limits of phase lock loop (PLL) FM demodulators. These limits establish the maximum deviation that the PLL can support (i.e., remain "inlock") based on the loop design parameters. The modulation limits are derived from experimental data on first and second order loops using sinusoidal and Gaussian noise modulation. The analysis of each PLL is broken into two regions, low frequency and high frequency modulation. It is shown that the deviation limit remains constant with modulation frequency for a first order loop in the low frequency region. In the high frequency region the deviation limit increases with increasing modulation frequency for both first and second order loops. The deviation limit in a second order loop increases with decreasing modulation frequency in the low frequency region and is a function of the loop damping.

The occurrence of cycle slipping in a Phaselock Loop (PLL) FM Demodulator is discussed. Single spikes occur in a first order loop as the modulation limit is exceeded with sinusoidal modulation. A second order loop, however, experiences complete break-up, commonly referred to as bursting, of the demodulated output when the modulation limit is exceeded. An explanation is provided for the phenomenon and the result is generalized to ann-th Order PLL.

A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null. Restoring force is small in the vicinity of the reverse null, and noise causes the loop to equivocate about the null. Hangup is very troublesome when fast acquistion is needed with high reliability. One example is synchronization of digital communications. Hangups can be avoided if a large restoring force is applied for large phase errors and if equivocation is prevented. An implementation of an antihangup circuit is proposed.

The design of 60 Mbit/s/180 Mbit/s time-division multiple-access (TDMA) channels for the European Communication Satellite (ECS) system is analyzed and a possible configuration is suggested [1]. The effects of adjacent-channel interference, nonlinear power amplifiers both on the ground and in space, uplink and downlink noise are investigated and results are shown. Methods for carrier recovery are investigated and comparisons made. The complete channel design includes pulse-shaping filters, satellite filters, limiters before each TWT, and a filter after the earth-station TWT to limit the radiated spectrum.