Adopting a new technology, such as a new storage system, is a complicated process because the supporting ecosystems also have to be changed. As a result, any new technology requires exhaustive performance evaluation to justify the cost of switching. However, synthetic workloads or benchmarks typically cannot completely characterize the actual workload. On the other hand, the time and effort required to obtain an appropriate trace can be prohibitive. This work presents a block-level performance measurement tool for storage systems combined with a trace re- player, a trace characteristics analyzer, and a trace re-generator. This new tool is compatible with several different platforms, including Linux and AIX. The purpose of the tool is to evaluate system performance when executing a given application, and to help users determine which system best fits their specific application. Additionally, the trace analyzer can provide details about the characteristics of a given trace. Using the trace analysis results, the re- generator can produce arbitrarily long I/O traces to improve the accuracy of the performance evaluation. The tool also can be used to determine whether a particular system can be adapted to a specific application, and to make comparisons between systems.

Computation at the edge of a datacenter has unique characteristics; it deals with streaming data from multiple sources, often requiring repeated application of several standard algorithmic kernels. The demand for high data rates and power efficiency points toward hardware acceleration of key functions. These accelerators must be tightly integrated with general purpose computation to keep invocation overhead and latency low. The accelerators must be easy for software to use, and the system must be flexible enough to support evolving networking standards.

Silicon-On-Insulator (SOI) technology allows for high performance by eliminating latch up in bulk CMOS, improving the short-channel effect, and soft error immunity. However, the floating body effect in SOI devices and the resulting hysteresis poses major challenges for dynamic circuit designers. In this paper, we describe implementation of a 64-bit adder and some of the techniques used to overcome the parasitic bipolar discharge effect while maintaining performance.

The cache replacement policy is one of the factors that determines the effectiveness of cache memories. We study the impact of incorporating the cache block coherence state information in the random replacement policy in a shared memory multiprocessor. We assign replacement priority to each cache block within a set based on its state. To reduce the probability of replacing a recently accessed block and to adapt to the program's access patterns, we also associate with each set an MRU (Most Recently Used) state. The MRU state causes the lowest replacement priority to be assigned to the blocks in the same state as the MRU state. Our evaluations indicate that, with the appropriate priority assignment and a set associativity size less than 16, the proposed policy can outperform the Random and Random & Invalid policies and, in some cases, can even outperform the LRU policy.

We evaluate the performance impact of two different write-buffer configurations (one word per buffer entry and one block per buffer entry) and two different write policies (write-through and write-back), when using the partial block invalidation coherence mechanism in a shared-memory multiprocessor. Using an execution-driven simulator, we find that the one word per entry buffer configuration with a write-back policy is preferred for small write-buffer sizes when both buffers have an equal number of data words, and when they have equal hardware cost. Furthermore, when partial block invalidation is supported, we find that a write-through policy is preferred over a write-back policy due to its simpler cache hit detection mechanism, its elimination of write-back transactions, and its competitive-performance when the write-buffer is relatively large.

Cache coherence schemes that dynamically adapt to memory referencing patterns have been proposed to improve coherence enforcement in shared-memory multiprocessors. By using only run-time information, however, these existing schemes are incapable of looking ahead in the memory referencing stream. We present a combined hardware-software strategy that uses the predictive capability of the compiler to select updating or invalidating for each write reference. To determine the potential performance improvement that can be achieved with this optimization, three different levels of compiler capabilities are examined. Simulations using memory traces show that with an ideal compiler, this optimization can potentially reduce the miss ratio by 0.4% to 15% compared to an invalidating-only scheme, while reducing the generated network traffic by 13% to 94% compared to an updating-only scheme. In addition, this optimization can potentially reduce the miss ratio by up to 13%, while reducing the generated network traffic by up to 92%, compared to a dynamic adaptive scheme. Furthermore, performance can be potentially improved even with a compiler capable of performing only imprecise array subscript analysis and no interprocedural analysis.>

Both hardware-controlled and compiler-directed mechanisms have been proposed for maintaining cache coherence in large-scale shared-memory multiprocessors, but both of these approaches have significant limitations. We examine the potential performance improvement of a new software-hardware controlled cache coherence mechanism. This approach augments the run-time information available to a directory-based coherence mechanism with compile-time analysis that statically identifies write references that cannot cause coherence problems and writes that should be written through to memory. These references are marked as not needing to send invalidation messages to thereby reduce the network traffic produced by the directory while maintaining cache consistency. For those memory references that are ambiguous, due to conditional branches, or due to the need for complex data flow analysis, for instance, the compiler conservatively marks the references and relies on the hardware directory to ensure coherence. Trace-driven simulations are used to emulate the compile-time analysis on memory traces and to estimate potential performance improvement that could be expected from a compiler performing this optimization on the Perfect Club benchmark programs. By reducing the number of invalidations, this optimized directory scheme is capable of reducing the processor-memory network traffic by up to 54 percent compared to an unoptimized directory mechanism. In addition, the overall miss ratio can be reduced up to 42 percent due to a corresponding reduction in the number of write misses.