The resistive switching (RS) technology has many promising applications, but the inherent variability of RS devices has been an important obstacle for the progress towards mass production. Nonidealities of device switching performance have been widely modeled so far, and device degradation has been addressed through testing for fault diagnosis. However, online soft-error “prognosis” concerning both the progressive degradation and transition faults, has been given little consideration. In this direction, we present preliminary results towards the development of prognostics and system health management (PHM) techniques for resistive memory (ReRAM) applications. We propose addressing soft errors through a rich in context scheme used to encode binary information in form of resistance. In out simulations we assumed a ReRAM driver with multi-level READ capability and developed an enhanced progressive feedback-WRITE scheme to ensure not only successful WRITE and reliable READ operations, but also to permit the early online prognosis of potential device failure. Preliminary system-level simulation results validate the expected functionality and represent a reasonable approach towards the design of robust ReRAM controllers.

The intrinsic behavioral variability in resistive switching devices (also known as "memristors" or "ReRAM devices") can be a reliability limiting factor or an opportunity for applications where randomness of resistance switching is essential, such as hardware security and stochastic computing. The realistic assessment of ReRAM-based circuits & systems towards practical exploitation requires variability-aware ReRAM modeling. In this context, here we present a versatile, circuit-level implementation strategy to incorporate cycle-to-cycle (C2C) variability to the ReRAM model parameters in SPICE simulations. We evaluated the proposed approach with threshold-based models of a voltage-controlled bipolar ReRAM device and managed to reproduce the main features observed in experimental curves for different pulsed voltage inputs. With key upgrades, compared to previous approaches found in the literature, our strategy enables the enhancement of any ReRAM device model towards the exploration of new ways to make the most of the C2C ReRAM variability, and to test the robustness of any designed circuits & systems against ReRAM variability.

The use of computational memories based on ReRAM technology is currently being explored for the next-generation energy-efficient computing-in-memory (CIM) systems. Such approach presents major challenges at device, circuit, and application level. Thus, this MSc Thesis work aims to establish a roadmap towards technologically-viable solutions for the design and development of industrially appealing ReRAM-based CIM systems. To this end, we comment on the major steps in the SW-HW co-design to develop the memory array driving circuitry that will support memory and logic operations based on non-stateful logic primitives. The latter are expected to be variability-agnostic and not to rely computations on probabilistic switching of memristors. Furthermore, we highlight the requirement for synthesis algorithms designed ad-hoc for CIM systems, compatible with the peripheral circuitry of the ReRAM and the underlying logic primitives, which will produce delay/area-efficient execution of an arbitrary logic function in memory. The complete toolkit resulting from the proposed roadmap is expected to accelerate the industrial establishment of resistive CIM systems through the development of functional prototypes, fully compatible with imperfections of ReRAM devices, thus useful for immediate practical exploitation by the relevant industry.

Resistive RAM (ReRAM) technology is continuously maturing and it is attracting important investments towards more energy-efficient computing systems. Recent approaches to ReRAM-based computing consider the inmemory computations equivalent to memory read operations. In this context, here we summarize a nonstateful ratioed logic style and guide the reader through the design of a computational 1T1R ReRAM module supporting reliable, variability-tolerant, and device technology-independent in-memory logic operations. We present circuit simulations of a 1-bit Full Adder to validate the robustness of the multi-level ratioed logic computations. Moreover, we underline the advantageous performance of nonstateful ratioed logic compared to stateful logic alternatives. Through a common ground basis used to simplify comparisons by translating computing steps/cycles into memory read/write operations, we found promising results in terms of delay and energy consumption compared to performance of stateful logic counterparts. Such results highlight the important benefits gained by basing all in-memory logic computations on memory read operations instead of conditional write operations.

Development of memristor device models is a research topic of utmost interest. As the resistance switching mechanism is not always known in all details, several “behavioral” models employ window functions (WFs) to improve accuracy and to capture the switching-rate dependency on the bias conditions. The WFs published so far are functions of just the state variable(s), whose effectiveness was tested in fitting typical hysteretic i-v characteristics, ignoring the effect of the applied signal magnitude in dynamic behavior. In this context, we introduce a generalized concept of bias-dependent WFs, designed to enhance simple behavioral models by making possible capturing rich dynamic time-response of memristors. An implementation example is presented and its effect on the response of a threshold-based model of a voltage-controlled bipolar memristor is evaluated in simulations with LTSPICE.

It has been shown that networks of memristors are promising as computing medium for the solution of complex optimization problems. In this context, the solution to the shortest-path problem (SPP) in a two-dimensional plane has been given wide consideration. Some still open problems in such computing approach concern the time required for the network to reach to a steady state, and the time required to read the result, stored in the state of a subset of memristors that represent the solution. This paper presents a circuit simulation-based performance assessment of memristor networks as SPP solvers. A previous methodology is extended to support weighted directed graphs. We use memristor device models with fundamentally different switching behavior, to check their suitability for such applications. Furthermore, the requirement of binary vs. analog operation of memristors is evaluated. Finally, this approach is compared to known algorithmic solutions to the SPP over a set of large random graphs. Our results contribute to the development of bio-inspired memristor network-based SPP solvers.

Resistive switching devices -memristors -present a tunable, incremental switching behavior. Tuning their state accurately, repeatedly and in a wide range, makes memristors well-suited for multi-level (ML) resistive memory cells and analog computing applications. In this brief, the tuning approach based on a memristor-resistor voltage divider (VD) is validated here experimentally using commercial memristors from Knowm Inc. and a custom circuit. Rapid and controllable multi-state SET tuning is shown with an appreciable range of different resistance values obtained as a function of the amplitude of the applied voltage pulse. The efficiency of the VD is finally compared against an adaptive pulse-based tuning protocol, in terms of circuit overhead, tuning precision, tuning time, and energy consumption, qualifying as a simple hardware solution for fast, reliable, and energy-efficient ML resistance tuning.

Nonlinear circuits may be interconnected and organized in networks to couple their dynamics and achieve synchronization, a process that is commonly observed in nature. Recent works have shown that memristors may be used as coupling elements in synchronization applications. However, these devices may suffer from low endurance and thus switching faults. Hence, evaluating redundancy and adaptive properties against possible device failures is important. In this direction, we study the performance of a network of chaotic circuits that are coupled using memristors organized in a crossbar geometry. This topology is analyzed in terms of robustness while assuming the existence of defective coupling devices. Our simulation results, based on a physics-based model of bipolar memristor, demonstrate the adaptive behavior of the crossbar architecture and show evidence of different network topologies whose performance outperforms that of the fully functional crossbar.

The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied pulse characteristics, such as amplitude and duration. However, parameter variability holds back any universal approach based on these two magnitudes, making also difficult even the qualitative comparison between different RS material compounds. On the contrary, there is a relevant magnitude which is much less affected by device variability; the energy. In this direction, we doubt anyone so far has ever wondered “what is the quantitative effect of the injected energy on the device state?” Interestingly, a first step was made recently towards the definition of performance parameters for this emerging device technology, using as fundamental parameter the energy. In this work, we further elaborate on such ideas, proving experimentally that the “resistance change per energy unit” $( dR/ dE )$ can be considered a significant magnitude in analog operation of bipolar memristors, being a key performance parameter worth of timely disclosure.

Cellular Automata (CA) is a nature-inspired and widespread computational model which is based on the collective and emergent parallel computing capability of units (cells) locally interconnected in an abstract brain-like structure. Each such unit, referred as CA cell, performs simplistic computations/processes. However, a network of such identical cells can exhibit nonlinear behavior and be used to model highly complex physical phenomena and processes and to solve problems that are highly complicated for conventional computers. Brain activity has always been considered one of the most complex physical processes and its modeling is of utter importance. This work combines the CA parallel computing capability with the nonlinear dynamics of the memristor, aiming to model brain activity during the epileptic seizures caused by the spreading of pathological dynamics from focal to healthy brain regions. A CA-based confrontation extended to include long-range interactions, combined with the recent notion of memristive electronics, is thus proposed as a modern and promising parallel approach to modeling of such complex physical phenomena. Simulation results show the efficiency of the proposed design and the appropriate reproduction of the spreading of an epileptic seizure.

Unconventional computing has been studied intensively, even after the appearance of CMOS technology. Currently, it has returned to the spotlight because CMOS is about to reach its physical limits, given that the constant demand for more computational power requires for novel unconventional computing solutions. In this area, the oscillatory internal motion mechanism of slime mould, namelyPhysarum Polycephalum, could serve as an alternative concept for the design and development of electronic circuits that exploit the memristive dynamics and simple LC contours to deliver solutions for computationally hard to be solved problems. In this direction, this work presents how bio-inspired memristive LC oscillators with a coupling capacitor can be synchronized to perform the functionalities of a biological neuron, also able to execute more complex computations, aiming to model biological neural systems much more advanced than the neuron-less slime mould biological organism. This work proposes a connection between the function mechanism of a simple biological organism and that of complex biological systems, made in a plausible and sufficient manner, towards unconventional computation with memristors.

This paper presents a fully digital implementation of a memristor hardware (HW) simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field-programmable gate array families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks, implementing examples of associative memory and unsupervised learning of spatiotemporal correlations in parallel input streams using a simplified spike-timing-dependent plasticity. We provide the full circuit schematics of all our digital circuit designs and comment on the required HW resources and their scaling trends, thus presenting a design framework for applications based on our HW simulator.

Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable applications is in the memory system field. Despite their promising characteristics and the advancements in this emerging technology, variability and reliability are still principal issues for memristors. For these reasons, exploring techniques that check the integrity of circuits is of primary importance. Therefore, this paper proposes a method to perform an on-line test capable to detect a single failure inside the memory crossbar array.

Resistive random access memory (ReRAM), referred to as memristor, is an emerging memory technology to potentially replace conventional memories, which will soon be facing serious design challenges related to continued scaling. Memristor-based crossbar architecture has been shown to be the best implementation for ReRAM. However, it faces a major challenge related to the sneak current (current sneak paths) flowing through unselected memory cells, which significantly reduces the voltage read margins. In this paper, five alternative architectures (topologies) are applied to minimize the impact of sneak current; the architectures are based on the introduction of insulating junctions within the crossbar. Simulations that were performed while considering different memory accessing aspects, such as bit reading versus word reading, stored data background distribution, crossbar dimensions, etc., showed that read margins can be increased significantly (up to 4×) as compared with standard crossbar architectures. In addition, the proposed architectures eliminate the requirement for extra select devices at each cross point and have no operational complexity overhead.

Within an ever-increasing variety of applications for memristors, adaptive electronic circuits have attracted considerable attention lately. This paper extends previously published work on memristive filter design to include the potential of composite memristive devices as damping elements in LC-based sensing circuits. The collective response of several LC contours with different memristive damping is considered. A thorough study of the circuit properties is performed in an attempt to exploit the high sensitivity of the circuit, other than address it as a typical drawback. The simulated circuits could find application in bio-inspired information processing, whereas could lead to better behavioral models for biological organisms.

Simulation is expected to become an indispensable educational and research tool for memristive circuits and architectures. To this end, this paper presents a novel, self-contained, platform-independent, GUI-based design and simulation tool for standard/alternative memristive crossbar architectures, targeting memory and/or logic applications. It permits the exploration of the crossbar-based memristive circuit design-space and allows for logic-in-memory computations.

This Live Demonstration is about an interactive software tool developed by the present authors. The tool will run on a personal laptop which the demonstrator will be responsible to bring to the conference site. There are no further special requirements and the mentioned provisions in the presentation booths, i.e. a power plug, a table, and a pin wall, are sufficient.

Memories based on hysteretic resistive materials are expected to have superior properties such as nonvolatility, low power consumption, as well as very high capacity. Crossbar arrays are considered very attractive for future ultimately scaled memories. In this paper, the memristor-based passive crossbar geometry is studied and a set of different topological patterns, which introduce insulating junctions within the memory array, is presented. In the worst-case reading scenario the simulations revealed significantly improved sensed voltage margins (up to > 4×) which alleviate the rigorous requirement for large and highperformance CMOS sensing circuits in passive crossbar memory systems.