As the integration level of integrated circuits continues to increase and the feature size of nanoscale chips continues to shrink, the possibility of triple-node-upsets (TNUs) occurring in circuits increases significantly. This paper proposes a latch, namely CLTNUSL, which offers stable resilience against TNUs in radiative environments while achieving a good balance between reliability and overhead. Unlike the conventional latches consisting of multi-input C-elements, the proposed CLTNUSL latch mainly consists of 16 interlocked dual-input inverters. Due to the small number of transistors, CLTNUSL achieves low area overhead. Due to the use of high-speed paths and clock gating techniques, CLTNUSL achieves low latency and low power consumption. Simulation results demonstrate CLTNUSL’s full recovery from TNU in all scenarios. Compared with the conventional TNU-hardened latch, CLTNUSL achieves minimal latency, power consumption, area overhead, and the delay-power-area product (DPAP). CLTNUSL reduces delay by 13.22%, power by 52.74%, area by 40.90%, and DPAP by 71.44% on average, compared with state-of-the-art latches. Process-Voltage-Temperature (PVT) and Monte Carlo simulation results show that the CLTNUSL latch is less sensitive to temperature, voltage and process variations compared with conventional TNU self-recovery latches.

This paper presents a radiation-tolerant voltage reference circuit based on atomic layer-deposited zinc oxide thinfilm transistors (ZnO TFTs), where both active and floating gate layers utilize ZnO films. Employing a dual-exponential current source method, we accurately simulate single-event transient currents induced by high-energy particles. Measurement results demonstrate that the proposed circuit achieves $5 \mu \mathrm{~s}$ recovery time without radiation hardening, reducible to $1 \mu \mathrm{~s}$ with hardening techniques. The circuit generates a 3.1 V reference voltage operating from 6 V to 10 V supply, with $18.78 \mathrm{mV} / \mathrm{V}$ line sensitivity and $0.72 \mu \mathrm{~W}$ static power consumption. Temperature stability is achieved through a complementary temperature coefficient. From $0^{\circ} \mathrm{C}$ to $80^{\circ} \mathrm{C}$, the temperature coefficient of VREF is $79.56 \mathrm{ppm} /{ }^{\circ} \mathrm{C}$, and the PSRR reaches -36.5 dB.

This paper proposes a novel Agile Physical Compiler (APCer) for multi-port register files based on a standard cell library. It employs a Performance, Power and Area (PPA)-driven genetic algorithm to facilitate agile iterations and design generation. APCer can automatically iterate, generate, and optimize floorplan, rapidly creating efficient register file circuits and layouts with specified capacity and port numbers. Additionally, APCer responds to user-defined PPA requirements, enabling targeted design optimizations. It accelerates the register file design duration by over 40× and 20× compared with the full custom approach and existing compilers, respectively. Compared to existing compilers, APCer improves performance by 20.7% and reduces power consumption by 33.9%. Compared to the full custom approach, APCer improves performance by 31.5% and reduces power consumption by 28.8%.

The state of the art analog circuit design applies mainly a full-custom layout methodology. This demands high expertise and heavy manual workload. Additionally, neither can the resulting layout be re-used easily across different designs or different PDKs. Learning from digital standard cells, existing work has proposed stem cells that are abuttable. But stem cells have a fixed area ratio of 2 over same-sized Pcells, limiting its wide application. In this paper we develop a new type of abuttable analog cells (called Acells) for transistors and passive elements. Acells are compatible with digital standard cells and can be abutted in all directions, enabling the use of automatic digital place and route (PnR) engines. We automate Acell generation and show that the average area ratio over same-sized Pcell is 1.49 for 65nm technology and 1.3 for 28nm technology, and is expected to decrease for more advanced technologies. We then use digital PnR to automatically layout a number of analog and mixed-signal (AMS) circuits mainly in 28nm, and show that compared to Pcell-based manual layout, Acell-based layout obtains similar performance and its circuit level layout area is about 2% higher for large scale AMS circuits in our experiments.

This article proposes a novel and effective 14-transistors (14T) reconfigurable radiation-hardened static-random access-memory cell design under the SMIC 65-nm process, featuring a unique memory reconfigurability architecture with two operation modes, namely the high reliability (HR) mode and the triple-time memory (TTM) mode for meeting different radiation environmental requirements. The proposed HR mode provides strong protection of the memory arrays in harsh radiation environments. Compared with the traditional triple modular redundancy (TMR) structure, the proposed HR mode reduces area overhead by 30%, delay by 37%, and power consumption by 16%. The TTM mode uses the enable (EN) circuit to expand the capacity threefold in less harsh radiation environments, avoiding the area wastage caused by the traditional TMR structure. By implementing the two innovative operation modes, the proposed design overcomes the limitations of the traditional TMR structure, reducing area overhead while retaining the radiation hardening capability. In addition, this article presents a mode-switching mechanism composed of a detection circuit and an EN circuit. The detection circuit can detect errors in the reconfigurable architecture. With the proposed mode-switching mechanism, two operation modes can switch in response to different radiation environments. Besides, to ensure the normal operations of the TTM mode in radiation environments, the proposed 14T cell serves as a bitcell in the memory reconfigurable architecture. Compared with typical existing designs, such as radiation-hardened based design, writability enhanced, and dual interlocked storage cell (DICE) cells, the proposed 14T cell design has better delay, critical charge, and higher hold static noise margin.

With the advancement of semiconductor technology, circuits have become increasingly susceptible to errors induced by radiation. Traditional approaches to enhancing the resilience of circuits against single-node upsets (SNUs) are insufficient to meet the robustness standards of modern designs. This article proposes a high-performance, low-power latch, named high-performance low-power double-node upset resilient latch (HLDRL), which is designed to exhibit exceptional resilience against double-node upsets (DNUs). Its design has six intricately interconnected C-elements (CEs) and two three-input CEs, for error interception, ensuring robust performance even in the case of DNUs. The Technology Computer Aided Design (TCAD) tool is used to validate the effectiveness of the HLDRL. Besides, comprehensive simulations are conducted utilizing the advanced SMIC 55-nm process technology. These simulation results show that our proposed HLDRL latch can autonomously recover from any DNU and thereby ensure the integrity of the system. Moreover, compared with existing DNU-resilient latches, the proposed HLDRL latch exhibits substantial improvements in terms of multiple metrics. On average, the proposed latch achieves an impressive 29.39% dynamic power saving, a remarkable 40.04% increase in speed, a notable 4.81% reduction in area, and a substantial 53.96% decrease in the power-delay–area product (PDAP). In the post-layout simulation, the proposed latch achieves a 30.39% dynamic power saving, a 36.47% increase in speed, and an impressive 52.38% decrease in PDAP. Furthermore, the proposed latch demonstrates enhanced resilience against variations in process, supply voltage, and temperature (PVT).

With the continuous advancement of CMOS technologies, soft errors, such as single-node upset (SNU) and double-node upset (DNU), caused by radiation in nanoscale integrated circuits, are becoming increasingly prominent. Meanwhile, transistor aging mitigation is indispensable for long-term robustness enhancement. First, to reduce the impact of radiation on circuits, we propose a novel DNU-recovery latch with low cost, namely, DURLC, only consisting of four dual-input C-elements (CEs) and four clock-gated input-split inverters for the storage of values. Second, we propose a DNU-recovery latch with moderate cost, namely, DURMC, based on seven CEs and four inverters, for convenience to optimize the latch to alleviate aging. The proposed DNU-recovery latch with mitigated aging is called DURMA. The latch employs a high-speed path to reduce delay without sacrificing performance when mitigating aging issues. Finally, we propose an algorithm-based verification method to validate the DNU recovery of the proposed latches. The simulation results show that, compared with the state-of-the-art robust latches, the proposed latches have the advantages of DNU recovery with moderate and even low cost, and meanwhile, aging is effectively mitigated for the DURMA latch.

Spintronic devices, such as magnetic tunnel junctions (MTJs), are promising for space applications due to their radiation hardness and nonvolatility. However, as semiconductor technology advances, CMOS peripheral circuits are becoming vulnerable to double node upset (DNU) as well as triple node upset (TNU). This brief proposes two nonvolatile and robust latch designs primarily composed of MTJs and C-elements (CEs). Both designs offer nonvolatility and self-recovery from multiple-node upsets. Simulation results demonstrate that the proposed latches provide nonvolatility and complete protection against multiple-node upsets with balanced overhead.

In nanoscale CMOS technology, harsh radiations in the environment can now easily cause soft errors, e.g., single-event transients (SETs) and triple node upsets (TNUs), severely affecting the reliability of space applications. In this article, TNUs tolerant and SET-pulses filtered latch (TUTPFL) with low power is proposed, which comprises from four input-stage C-elements (CEs), four inverters, and three output-stage CEs. The CEs’ delay differential enables the TUTPFL latch to effectively filter SET-pulse, while the CEs’ multilevel error-interception property enables the TUTPFL latch to tolerate any possible TNU. The results of HSPICE-based simulations and FPGA-based emulations demonstrate the TNU tolerance and SET filterability of the TUTPFL latch. Meanwhile, compared to the alternative radiation-hardened latches, the TUTPFL latch reduces power dissipation by roughly 20.43% on average.

Low-energy, radiation-hardened chips play a crucial role in the application of aerospace electronic equipment. This is because aerospace chips are susceptible to soft errors caused by single event upsets (SEUs) from space particle bombardment, as well as impacts on energy efficiency. As a vital core component of chips, memory storage, its key nodes becoming more sensitive to technological advancement. Moreover, the limited energy supply of the anti-radiation chip and excessive power consumption can result in an excessive burden on the thermal control system. In this paper, a low-energy-enhanced critical charge 16TSRAM (SAW16T) is proposed. To demonstrate the relative performance of SAW16T, the state of art technologies of other radiation-hardened memory cells, such as SARP12T, RH12T, RSP14T, EDP12T, SIS10T and SUR16T, are compared. Simulations are conducted at 27 °C using a 65-nm CMOS technology with a supply voltage of 1.2V. All sensitive nodes of SAW16T are able to recover to their initial states after being affected by soft errors. The critical charge of node Q hits 300fc under typical (tt), slow (ss), and slow-N fast-P (snfp) process corners, whereas node S1's critical charge reaches 300fc in tt, fast (ff), ss, fast-N slow-P (fnsp), and snfp process corners, tripling the reference value in literature. SAW16T exhibits the shortest write access time compared to the aforementioned cells, with hold power consumption reduced by 99.9%, 49.95%, 43.8%, 21.6%, and 62.9%, compared to RH12T, RSP14T, EDP12T, SIS10T, SUR16T, respectively. Furthermore, SAW16T has been demonstrated superior performance in comprehensive performance evaluations.

As technology scales down, the critical charge (QC) of vulnerable nodes decreases, making SRAM cells more susceptible to soft errors in the aerospace industry. This article proposes a Soft-Error-Aware 16T (S8P8N) SRAM cell for aerospace applications to address this issue. The properties of S8P8N are evaluated and compared with 6T, DICE, QUCCE12T, WEQUATRO, RHBD10T, RHBD12T, S4P8N, SEA14T, and SRRD12T. Simulation results indicate that all vulnerable nodes and key node pairs of the proposed cell can recover to their original states when affected by a soft error. Additionally, it can recover from key multinode upsets. The write speed of the proposed cell is found to be reduced by 20.3%, 50.1%, 74.1%, 63.7%, and 50.41% compared to 6T, DICE, QUCCE12T, WEQUATRO, and RHBD10T, respectively. The read speed of the proposed cell is found to be reduced by 56.6%, 52.2%, 62.5%, and 35.2% compared to 6T, SRRD12T, RHBD12T, and S4P8N, respectively. It also shows that the hold power of the proposed cell is found to be reduced by 14.1%, 13.8%, 17.7%, and 23.4% compared to DICE, WEQUATRO, RHBD10T, and RHBD12T. Furthermore, the read static noise margin (RSNM) of the proposed cell is found to be enhanced by 157%, 67%, and 32% compared to RHBD12T, SEA14T, and SRRD12T. All these improvements are achieved with a slight area penalty.

There are two primary defects in the existing UAV avoidance systems: the system is memoryless; airborne radars are used to detect long‐distance barriers, which are unreliable and expensive. The paper adopts the deep learning algorithm and ADS‐B communication system based on a satellite base station to solve the above problems. It divides the avoidance problem into two parts: short‐distance obstacle avoidance and long‐distance route planning. On the one hand, the system establishes the knowledge base storing the previous avoidance experience and the matching mechanism, realizing the correspondence between input and experience through a deep learning algorithm. They can dramatically improve the reaction speed and safety of UAVs. On the other hand, the system realizes the interconnection between UAV and the satellite base station through the ADS‐B communication system to replace the radars, putting the task of route planning on the satellite platform. Therefore, the satellite can achieve large‐scale and all‐weather detection to improve the overall safety of UAVs depending on its high and long‐range characteristics. The paper also illustrates the design elements of the RF baseband integrated ADS‐B transceiver and the simulation performance of the short‐distance avoidance system in the end, whose results show that the system can be applied to dense obstacle environments and significantly improve the security of UAVs in a complex domain.

The leakage current existing in the bitline of SRAM has attracted more and more concerns for the operation of high-performance SRAM design, especially with the decrease of the threshold voltage of the transistor for high-performance demand, the leakage current would increase exponentially. The increased leakage current may slowdown the performance of the read operation of SRAM because the existence of the leakage current in the bitline may postpone the time to resolve the sufficient differential bitline voltage for SA to sense correctly. In this paper, a new bitline leakage current compensation circuit has been proposed. Different from the traditional technique, the proposed bitline leakage current compensation circuit cancels the "pre-determined" leakage current compensation process. Therefore, it dodges the dilemma where the performance of the SRAM may be degraded in some circumstances if the bit-line leakage current is compensated pre-determinedly. The simulation results show that by adopting the proposed compensation circuit, the time needed to develop 1/2 VDD can be reduced by almost 126.4% under the tt process corner.