Many currently available deep neural network (DNN) accelerators are highly application specific and have focused on supervised learning. In addition, many accelerators have rigid architectures and algorithms that prevent adapting to dynamic environments. In this work, we propose a neuromorphic architecture implementing a self-organizing feature map (SOFM) using ferroelectric field-effect transistors (FeFETs) for in-memory error computation. The neuromorphic architecture takes inspiration from biological networks and is able to grow neurons to adapt to the application. Furthermore, it is able to modulate the distance between neurons to provide more fluidity to its topography. We demonstrate that the ability of the network to adapt to various datasets and even exhibit lifelong learning and self-repair. We further demonstrate the architecture's efficiency in terms of both power and speed as well as its robustness to device variability.

Software defined radio (SDR) provides significant advantages over traditional analog radio systems and are becoming increasingly relied on for ”mission critical” applications. This along with risk of trojans, single-event upsets and human error creates the necessity for fault tolerant systems. Redundancy has been traditionally used to implement fault tolerance but incurs a substantial area overhead which is undesirable in most applications. Advancements in field-programmable gate array and system on a chip technologies have made implementing machine learning (ML) algorithms within embedded systems feasible. In this paper we explore the use of ML to implement fault tolerance in an SDR. Our approach, which we call adaptive component-level degeneracy (ACD), uses a ML model to learn the functionality of an SDR component. Once trained, the model can detect when the component is compromised and mitigate the issue with its own output. We demonstrate the ability of our model to learn multiple simulated SDR components. We compare the one-dimensional convolutional neural network and bidirectional recurrent neural network architectures at modeling time series components. We also implement ACD within a real-time SDR system using GNU Radio Companion. The results show great potential for the utilization of ML techniques for improving embedded system reliability.

This work reports a spiking neuromorphic architecture for associative memory simulated in a SPICE environment using recently reported gated-RRAM (resistive random-access memory) devices as synapses alongside neurons based on complementary metal-oxide semiconductors (CMOSs). The network utilizes a Verilog A model to capture the behavior of the gated-RRAM devices within the architecture. The model uses parameters obtained from experimental gated-RRAM devices that were fabricated and tested in this work. Using these devices in tandem with CMOS neuron circuitry, our results indicate that the proposed architecture can learn an association in real time and retrieve the learned association when incomplete information is provided. These results show the promise for gated-RRAM devices for associative memory tasks within a spiking neuromorphic architecture framework.

Repetitive occupational lifting has been shown to create an increased risk for incidence of back pain. Ergonomic workstations that promote proper lifting technique can reduce risk, but it is difficult to assess the workstations without constant risk monitoring. Machine learning systems using inertial measurement unit (IMU) data have been successful in various human activity recognition (HAR) applications, but limited work has been done regarding tasks for which it is difficult to collect significant amounts of data, such as manual lifting tasks. In this article, we discuss why traditional methods of data expansion may fail to improve performance on IMU data, and we present a machine learning system capable of detecting lifting action for assessing the risk for back pain using a relatively small amount of data. The proposed models outperform baseline HAR models and function on raw time-series data with minimal preprocessing for efficient real-time application.

The rising trend and advancements in machine learning has resulted into its numerous applications in the field of computer vision, pattern recognition to providing security to hardware devices. Eventhough the proven achievements showcased by advancement in machine learning, one can exploit the vulnerabilities in those techniques by feeding adversaries. Adversarial samples are generated by well crafting and adding perturbations to the normal input samples. There exists majority of the software based adversarial attacks and defenses. In this paper, we demonstrate the effects of adversarial attacks on a reconfigurable RRAM-neuromorphic architecture with different learning algorithms and device characteristics. We also propose an integrated solution for mitigating the effects of the adversarial attack using the reconfigurable RRAM architecture.

This work reports a compact behavioral model for gated-synaptic memory. The model is developed in Verilog-A for easy integration into computer-aided design of neuromorphic circuits using emerging memory. The model encompasses various forms of gated synapses within a single framework and is not restricted to only a single type. The behavioral theory of the model is described in detail along with a full list of the default parameter settings. The model includes parameters, such as a device's ideal set time, threshold voltage, general evolution of the conductance with respect to time, decay of the device's state, etc. Finally, the model's validity is shown via extensive simulation and fitting to experimentally reported data on published gated-synapses.

Resistive Random-Access Memory (ReRAM) devices have caught significant research attention as scalable nonvolatile memory technology for high-density data storage in 3-D crossbar architectures. ReRAM devices can switch with low programming voltages (<; ±1 V) at fast time-scales (≈10-100 ns) that make them an attractive option for not only off-chip data storage but also for on-chip embedded memory applications. ReRAM devices have also been explored for applications as reconfigurable switches in field programmable gate arrays (FPGAs). The random variabilities in the switching performance of ReRAM has been exploited to design Physically Unclonable Function (PUF) for hardware authentication, trust, and security. However, intrinsic vulnerabilities in ReRAM devices and its implications are not well-understood. Therefore, there is an urgent need to understand these so that the ReRAM-based circuits can be made robust against such attacks. This paper discusses our research on understanding the vulnerabilities in ReRAM through experimental studies and its implications on ReRAM based PUF operations. The Process, Voltage, Temperature (PVT) variabilities in ReRAM is experimentally studied and modeled. Some other ReRAM specific vulnerabilities, such as insertion of parasitic capacitances and Trojans by adversaries and its impact on ReRAM switching behavior is discussed. Based on experimental studies, models are created to capture these behaviors in ReRAM. Using these models, a 1 KB array of ReRAM devices in a crossbar architecture and its behavior is simulated. The challenge-response pairs of these ReRAM-based arrays were studied under ideal Trojan free conditions as well as with vulnerabilities models of ReRAM. Potential solutions are then proposed to make the PUF architecture and ReRAM devices more resistant to these vulnerabilities.

We report a realization of a mixed-signal, supervised spiking neural network (SNN) architecture utilizing short-term plasticity in synaptic resistive random access memory (RRAM). First, the development of a phenomenological RRAM SPICE model is discussed based on the previously reported device data. Then, the design of the neuroprocessor's architectural components are described. To achieve learning using the synaptic RRAM devices, a novel method of backpropagation in hardware SNNs is presented using the proposed gated bidirectional amplifier circuit. A method to perform quantized weight transfer between the short-term memory (STM) and long-term memory (LTM) is also proposed, allowing transient associated memories to be stored and used repeatedly. The neuroprocessor is able to associate input digits with class labels, transfer learned associations to a long-term register array, then recall all digits when presented again. The low operational power of 13.7 mW makes this system ideal for future integration onto embedded systems with limited available energy. Finally, the neuroprocessor's tolerance to input noise and internal device failure was measured to be 14% and 15%, respectively. We believe that this work provides significant insight into the development of hardware SNNs in addition to providing a framework to achieve more complex STM to LTM interactions in the future.

Nature-inspired approaches have been widely used for different purposes over the last two decades and are still extensively researched, especially for complex real-world problems. Biological systems, or nature in general, serve as the source of the intelligence of nature-inspired approaches. The efficiency of nature-inspired approaches is due to their significant ability to imitate the best features of nature that evolved by natural selection over millions of years. These approaches have been successfully used for Internet of Things (IoT) and big data handling and relevant examples of these topics may be artificial neural networks (ANNs) and deep learning applications. On this basis, the main theme of this special issue (SI) addresses recent advances in the use of the nature-inspired approaches for IoT and big data problems.

We discuss the theory of gated memristive devices, which exhibit continuous states over three orders of magnitude and can be programmed independently of reading. A model is generated by using knowledge of the device physics and fitting the parameters to measured data. The gate-controlled memristor simplifies the implementation of analog artificial neural network architectures significantly. Using this, a very simple architecture is presented, along with a simulation and its performance metrics. The simulated analog neural neural network is able to achieve 88.9 percent accuracy on the MNIST test set. The objective is to demonstrate the advantages that gated memristors can give to analog neural networks.