Error detection and correction code based on Redundant Residue Number System (RRNS) has a unique advantage that arithmetical processing errors can also be corrected. Existing algorithms for multiple residue digit error correction in RRNS require either large modulo operations to decode the magnitude of the residue digits or variable number of iterative computations to identify the locations of erroneous residue digits. This paper presents an efficient syndrome based multiple residue digit error detection and correction algorithm in RRNS. The received residue digits are divided into three groups from which seven error location categories are defined for all combinations of residue digit errors of any legitimate moduli set. Their error magnitudes are abstracted into three syndromes, which are used to identify the exact error location category and retrieve the residue digit errors concurrently from six lookup tables in no more than three cycles. The syndromes can be computed in parallel by small modulo subtractors, and their uniqueness criteria are proved to be easily fulfilled. The redundant residue space due to the uniqueness criteria can also be relaxed by increasing the number of syndrome computations and lookup tables used for the error decoding according to the number of information moduli.

The authors would like to point out the following correction in the total power consumptions recorded in Table IV of the published article[1]. The total power consumptions of the proposed design and the design[2]in comparison should be corrected as shown inTable I.

Efficient modular adders and subtractors for arbitrary moduli are key booster of computational speed for high-cardinality Residue Number Systems as they rely on arbitrary moduli set to expand the dynamic range. This paper proposes a new unified modular adder/subtractor that possesses a regular structure for any modulus. Compared to the latest modular adder/subtractor, which works for modulus in the forms of 2n±k, the proposed design is on average 10.81% faster and consumes 15.85% less hardware area and 2.51% lower power for n ranging from 4 to 8.

This paper presents a new algorithm for the correction of single residue digit error in Redundant Residue Number System. The location and magnitude of error can be extracted directly from a minimum size lookup table. This is made possible by the introduction of a new syndrome, which is proven to be unique for every different residue digit error with two criteria imposed on the choice of redundant moduli. The erroneous residue digit can be corrected by deducting the error digit retrieved from the lookup table indexed by the syndrome. Our proposed algorithm compares favorably against existing single residue digit correction algorithms, and is more amenable to hardware implementation.

Scaling is used for wordlength reduction in many DSP algorithms. Variable scaler provides greater flexibility than fixed scaler and allows for more efficient utilization of the dynamic range. Programmable magnitude scaling is extremely difficult to perform in RNS, let alone scaling of signed integer. To the best of our knowledge, no programmable signed integer scaler in RNS has been reported. What make sign integer scaling challenging is that sign detection is itself a problematic operation in RNS. This paper presents an algorithm that can selectively scale a signed integer in the three moduli set RNS {2n-1, 2n, 2n+1} by a power-of-two factor. The proposed architecture can be deemed as a signed RNS extension of the unsigned integer programmable power-of-two scaler for {2n-1, 2n, 2n+1}. On average, it reduces the area and total power consumption of the unsigned version by 27.4% and 30.3% with an average delay extension of slightly less than 20% to adjust the range of a residue after magnitude scaling.

Scaling is a problematic operation in residue number system (RNS) but a necessary evil in implementing many digital signal processing algorithms for which RNS is particularly good. Existing signed integer RNS scalers entail a dedicated sign detection circuit, which is as complex as the magnitude scaling operation preceding it. In order to correct the incorrectly scaled negative integer in residue form, substantial hardware overheads have been incurred to detect the range of the residues upon magnitude scaling. In this brief, a fast and area efficient 2nsigned integer RNS scaler for the moduli set {2n-1, 2n, 2n+1} is proposed. A complex sign detection circuit has been obviated and replaced by simple logic manipulation of some bit-level information of intermediate magnitude scaling results. Compared with the latest signed integer RNS scalers of comparable dynamic ranges, the proposed architecture achieves at least 21.6% of area saving, 28.8% of speedup, and 32.5% of total power reduction for n ranging from 5 to 8.

A novel non-iterative circuit for computing integer square root based on logarithm is proposed in the paper. Mitchell's methods are used for the logarithmic and antilogarithmic conversions. The proposed method merges two conversion stages into a single one to achieve better accuracy with a compact architecture. Hence, the circuit size and latency are reduced. Compared to an existing design based on the modified Dijkstra algorithm used in a coherent receiver, the proposed design is either 8 times smaller or 9 times faster for 16-bit integer input.