As conventional computers based on von Neumann architecture approach their physical and performance limits, unconventional computing paradigms such as Cellular Neural Networks (CellNNs) have emerged as promising platforms for real-time, massively parallel analog computation. However, conventional analog CellNNs suffer from scalability and power constraints due to large cell hardware overhead. This work investigates the integration of memristor-based crossbar arrays into CellNN architectures to address these limitations by exploiting their analog tunability, high density, and low power operation. A 1-Transistor-1-Memristor (1T1R) crossbar is proposed for implementing the coupling weights defining the CellNN gene. Device nonlinearity, asymmetry and stochastic variability are incorporated using the physics-based JART VCM memristor model, enabling accurate mapping of target weights onto memristor conductances through numerical optimization and differential-pair encoding. Simulations of edge detection tasks confirm high functional accuracy and robustness, while Monte Carlo analysis reveals variability’s impact, underscoring the need for variability-aware design of reliable memristor-CNN hardware.

Memristive devices are promising enablers for computing-in-memory architectures, offering reduced latency and energy consumption compared to conventional designs. Among these, the memristive device-based Cellular Nonlinear Network (M-CNN) provides a compact framework for universal computing, including image processing and neuromorphic computing. In this work, we investigate the use of IGZO-based devices exhibiting gradual switching as core elements of M-CNN cells. A simulation approach based on measured I-V-characteristics is developed to evaluate device–circuit interactions. We first analyze the limitations of the conventional M-CNN cell core, where asymmetric I-V-characteristics restrict voltage levels and accelerate device degradation. To address these issues, we propose a symmetrized cell that mitigates asymmetry, intrinsically limits cell voltage, and supports differential readout. The results demonstrate that gradual switching enables reliable distinction of input current levels while ensuring stable operation and reduced power consumption, thus paving the way for robust IGZO-based M-CNN implementations.

Realized memristors exhibit a unique phenomenon called the fading memory effect, where the memristor response to an AC signal is determined by its characteristics (waveform, amplitude, frequency, and DC offset) rather than the memristor initial conditions. Recently, a method for programming Hewlett Packard’s TaOxmemristor to a target state was proposed, involving configuring the DC offset of a high-frequency square-wave AC voltage input. This served as a basic application example that exploits fading memory in non-volatile memristors, but didn’t consider non-ideal effects. Here, we assess the method applicability in a HfOx-based VCM resistive switch from Forschungszentrum Julich incorporating a variability-aware physics-based model.

We have successfully fabricated one of the earliest array-scale prototypes of a Memristive Cellular Nonlinear Network (M-CNN) with interconnected cells. In this live demonstration, we will showcase the operation of this 4x4 M-CNN array performing an edge detection task according to our previous work [1]. A user-defined input will be applied to the network, and the computing results will be visualized alongside the simulated operation of a standard CNN for comparison.

Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Scouting or Majority have been proposed for the implementation of logic Computing-in-Memory based on active 1T-1R crossbar arrays. The operation reliability of these concepts critically depends on the accurate readout current distinction. In this paper, we perform experimental tests for several non-stateful logic gates based on transistor-coupled resistive devices (further denoted as 1T-1R) using HfOx as the insulating material. The focus of our investigation lies on the operation reliability and the influence of operation parameters. Based on our experimental findings, we conduct a thorough statistical analysis, assessing the reliability and outline the limitations of non-stateful 1T-1R logic functions for Computing-in-Memory.

Emerging non-volatile memories (eNVM) promise to solve the imminent von Neumann bottleneck by enabling future computing systems to utilize the computing-in-memory (CIM) paradigm offering exceptional energy efficiency and performance advantages. As Moore's law becomes obsolete, CIM architectures are prominent candidates to push the boundaries of existing computing systems and usher in a new generation of computing models, such as neuromorphic systems. Furthermore, conventional systems face another significant problem in addition to the von Neumann bottleneck. Hardware security threats (e.g., Rowhammer) have gained momentum and can expose an entirely pristine attack surface for adversaries. These vulnerabilities distinguish themselves by being particularly challenging to patch because their origin lies in the rigid hardware layout. Unfortunately, neuromorphic systems are no exception. We presented NeuroHammer as one of the first unique hardware security attacks on eNVMs, enabling an attacker to intentionally flip bits in memristive crossbar arrays. This article extends our previous results by thoroughly examining the underlying concepts leading to the NeuroHammer attack. First, we investigate memory access patterns to gain insight into the tangible impact of NeuroHammer. Second, we extend our simulation methodology to accommodate transistor/one resistive (1T1R) crossbar structures and prove the prevalence of the NeuroHammer attack. Finally, we discuss the real-world implications of NeuroHammer on CIM architectures.

Memristive devices can not only be used as nonvolatile memories but also enable computation-in-memory (CIM) computing paradigms. CIM architectures show prospects in significantly reducing the data interaction time and energy consumption between processors and storage, thus addressing the bottleneck problem of the von Neumann architecture. Additionally, the capability of memristive devices to store multiple (resistance) states in one cell offer vast potential for CIM’s multi-valued logic, as they greatly enhance data storage density and computational efficiency. In this study, a novel concept for ternary Łukasiewicz logic utilizing the voltage divider of two (anti-)serially connected memristive devices is proposed. As this approach does not require any switching in the computation process and features a straightforward circuit architecture, a low energy consumption per operation is achieved. In addition, the concept is crossbar-array compatible. The concept is validated by circuit simulations using the JART VCM v1b model that has been calibrated to experimental data of a Pt/Ta2O5/W memristive device.

Memristive devices offer energy and area efficient non-volatile data storage for data-intense Ternary Content Ad-dressable Memory (TCAM) architectures. However, depending on the storage implementation in the bitcell design, the matching functionality shows multiple undesired discharge effects leading to false look-up results. In particular, the ternary storage suffers during the look-up operation from a poor resistance ratio, match-line leakage and device variabilities. In this paper, we investigate the inherent, design-dependent limitations in the ternary state storage capability due to different memristive TCAM bitcell design parameters and device variabilities. We test these limits based on variability-aware device simulations and isolate crucial parameters for the optimization of memristive TCAMs.

In this paper, the design of an isolated Memristor Cellular Nonlinear Network (CNN) cell with discrete electronic elements is presented. The proposed versatile circuit allows for adjustable cell dynamical characteristics, controlled by design parameters, while the discrete element approach enables simple on-board implementation without the need for large-scale integration, which is necessary for testing hardware with individual fabricated memristors. A voltage-mode approach, that makes use of the diversity of operational amplifiers, is preferred here over a current-mode one that necessitates a large number of individual transistors. The dynamical properties of the system are initially investigated through the calculation of equilibrium points and further illustrated applying the concept of State Dynamic Routes (SDRs) for the cell assuming that the memristor dynamics are much slower than the capacitor voltage dynamics. Moreover, the effect of design parameters on the cell dynamics is being investigated, showing how the scaling of the operating voltage, as well as a plethora of CNN variants -i.e., the Chua-Yang and Full Range models-, can be implemented within the same design. Finally, the nonlinear conductance properties of real memristor devices are incorporated into the study, demonstrating interesting bifurcation phenomena between the cell monostability and bistability for specific parameter values.

For reproducible resistive switching in memristive devices, electroforming is a crucial process. However, a deeper understanding of the electroforming process is still lacking due to unavailability of a proper simulation tool. Here, we propose a physics-based compact model for the electroforming of valence change mechanism (VCM) memristive devices. The developed JART VCM Forming model is experimentally validated with the ZrOx-based memristive device. Furthermore, the electroforming process in different 1T1R memristive arrays is simulated with this model. The study shows that the electrical characteristics of each device in the array after the forming process are influenced by word/bit line series resistance. In addition, control effects depending on the channel width and applied gate voltage of transistor in the 1T1R cell are also investigated with the compact model simulation.

The field of neuromorphic computing is approaching an era of rapid adoption driven by the urgent need of a substitute for the von Neumann computing architecture. NEUROTEC I: “Neuro-inspired Artificial Intelligence Technologies for the Elec-tronics of the Future” project is an initiative sponsored by the German Federal Ministry of Education and Research (BMBF for its initials in German), that aims to effectively advance the foundations for the utilization and exploitation of neuromorphic computing. NEUROTEC I stands at its successful “final stage” driven by the collaboration from more than 8 institutes from the Jiilich Research Center and the RWTH Aachen University, as well as collaboration from several high-tech industry partners. The NEUROTEC I project considers the field interplay among materials, circuits, design and simulation tools. This paper provides an overview of the project's overall structure and discusses the scientific achievements of its individual activities.

Emerging non-volatile memory (NVM) technologies offer unique advantages in energy efficiency, latency, and features such as computing-in-memory. Consequently, emerging NVM technologies are considered an ideal substrate for computation and storage in future-generation neuromorphic platforms. These technologies need to be evaluated for fundamental reliability and security issues. In this paper, we present NeuroHammer, a security threat in ReRAM crossbars caused by thermal crosstalk between memory cells. We demonstrate that bit-flips can be deliberately induced in ReRAM devices in a crossbar by systematically writing adjacent memory cells. A simulation flow is developed to evaluate NeuroHammer and the impact of physical parameters on the effectiveness of the attack. Finally, we discuss the security implications in the context of possible attack scenarios.

Memristive devices, such as ReRAM devices, enable Computation-In-Memory operations such as vector-matrix multiplications, which are basic kernels for neuromorphic computing. These devices, however, suffer from parasitic sneak path currents in memory arrays, which make a satisfactory performance on large-scale arrays impossible. To overcome this issue, for example, a bipolar rectifying element (‘select device’) in series to a resistive switching device (1S1R) is introduced at each cross-point junction. In this work, we investigate the design of 1S1R arrays for VMM operations and show the impact of wire resistances on these operations. We derive guidelines that give a quantitative relationship between the array size, wire resistance values, resistance states of the ReRAM and the select device and resulting current levels.

As the cost of keeping Moore’s law alive is ever increasing, unconventional device and circuit concepts are being explored, both in industry and in academic research arena. Among the new devices being explored are two terminals redox-based memristive devices, which can function as both a nonvolatile memory and a computing element. For enabling Computation-in-Memory (CIM) concepts, these devices are generally integrated in a passive configuration or in an active configuration, where transistors are employed together with the memristive switches. However, the reliability and variability of the memristive devices might impact the performance of CIM circuits. In this work, we experimentally demonstrate the impact of device-to-device (D2D) and cycle-to-cycle (C2C) variability on a simple IMPLY logic gate realized in passive and active configurations. The experimental data is theoretically verified by a physics based Verilog-A model of the memristive devices. Our findings suggest that the success rate of the logic operation can be increased by exploiting the D2D variability in the memristive devices.

Cellular Nonlinear Networks (CNN) as a powerful paradigm is highly suitable for signal processing of multiple tasks, since they can execute cascaded processing operations in a one-layer array via real-time template updating. Their VLSI implementation by using the conventional CMOS-based integration technology, however, remains a big challenge. The memristive CNN (M-CNN) offers several merits over conventional CNN, such as compactness, nonvolatility, versatility. This paper presents a direct comparison of computing performance between the M-CNN and the conventional CNN for the implementation of a LOGAND operation template using circuit simulation. Our findings show that the M-CNN implementation offers rapid attainment of equilibrium state compared to the CNN implementation. In addition, the result is stored in a non-volatile manner in the M-CNN whereas the CNN only offers a volatile storage.

Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency, which is a promising approach to address so-called memory wall of conventional von Neumann architectures. Redox-based Random access memory (ReRAM) is an appropriate candidate for the realization of CiM concepts in CMOS co-integrated crossbar structures. However, ReRAM devices suffer from inherent variability in fabrication and operation. In this paper, we propose a statistical failure probability framework for the reliability evaluation of ReRAM-based CiM. Based on this, a comprehensive reliability analysis is performed for logic operations in ReRAM-based Scouting and MAGIC concepts at the crossbar level. Our proposed framework shows that existing logic operation in the crossbar architecture has a high failure probability due to the variability and crossbar non-idealities. Hence, a modified crossbar design is proposed to achieve the target reliability requirements.

Conventional von Neumann architectures cannot successfully meet the demands of emerging computation and data-intensive applications. These shortcomings can be improved by embracing new architectural paradigms using emerging technologies. In particular, Computation-In-Memory (CiM) using emerging technologies such as Resistive Random Access Memory (ReRAM) is a promising approach to meet the computational demands of data-intensive applications such as neural networks and database queries. In CiM, computation is done in an analog manner; digitization of the results is costly in several aspects, such as area, energy, and performance, which hinders the potential of CiM. In this article, we propose an efficient Voltage-Controlled-Oscillator (VCO)–based analog-to-digital converter (ADC) design to improve the performance and energy efficiency of the CiM architecture. Due to its efficiency, the proposed ADC can be assigned in a per-column manner instead of sharing one ADC among multiple columns. This will boost the parallel execution and overall efficiency of the CiM crossbar array. The proposed ADC is evaluated using a Multiplication and Accumulation (MAC) operation implemented in ReRAM-based CiM crossbar arrays. Simulations results show that our proposed ADC can distinguish up to 32 levels within 10 ns while consuming less than 5.2 pJ of energy. In addition, our proposed ADC can tolerate ≈30% variability with a negligible impact on the performance of the ADC.

In recent years, we are witnessing a trend toward in-memory computing for future generations of computers that differs from traditional von-Neumann architecture in which there is a clear distinction between computing and memory units. Considering that data movements between the central processing unit (CPU) and memory consume several orders of magnitude more energy compared to simple arithmetic operations in the CPU, in-memory computing will lead to huge energy savings as data no longer needs to be moved around between these units. In an initial step toward this goal, new non-volatile memory technologies, e.g., resistive RAM (ReRAM) and phase-change memory (PCM), are being explored. This has led to a large body of research that mainly focuses on the design of the memory array and its peripheral circuitry. In this article, we mainly focus on the tile architecture (comprising a memory array and peripheral circuitry) in which storage and compute operations are performed in the (analog) memory array and the results are produced in the (digital) periphery. Such an architecture is termed compute-in-memory-periphery (CIM-P). More precisely, we derive an abstract CIM-tile architecture and define its main building blocks. To bridge the gap between higher-level programming languages and the underlying (analog) circuit designs, an instruction-set architecture is defined that is intended to control and, in turn, sequence the operations within this CIM tile to perform higher-level more complex operations. Moreover, we define a procedure to pipeline the CIM-tile operations to further improve the performance. To simulate the tile and perform design space exploration considering different technologies and parameters, we introduce the fully parameterized first-of-its-kind CIM tile simulator and compiler. Furthermore, the compiler is technology-aware when scheduling the CIM-tile instructions. Finally, using the simulator, we perform several preliminary design space explorations regarding the three competing technologies, ReRAM, PCM, and STT-MRAM concerning CIM-tile parameters, e.g., the number of ADCs. Additionally, we investigate the effect of pipelining in relation to the clock speeds of the digital periphery assuming the three technologies. In the end, we demonstrate that our simulator is also capable of reporting energy consumption for each building block within the CIM tile after the execution of in-memory kernels considering the data-dependency on the energy consumption of the memory array. All the source codes are publicly available.

In the group of emerging non-volatile storage technologies, redox-based memristive devices stand out due to their possibility for extreme dense integration, low power consumption and multilevel capabilities. The opportunity to directly perform Boolean logic operations using memristive devices opens a promising path towards Computation-in-Memory. Recently 7- state memristive devices based on TaOx were used to realize a ternary adder circuit as well as a ternary Łukasiewicz logic and fuzzy logic. Logic that uses more than two truth values promises to reduce the number of devices that are needed for a certain operation and thereby further increases the integration density. In this work, we propose a multinary logic for three, five and seven truth values based on the Łukasiewicz logic and show the performance for the implication and negation operation. We, therefore, used the physics-based compact model JART VCM v1b to describe the relation between RESET voltage and high resistive state and then performed the logic operations.

Abstract Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective production, will become infeasible below a certain feature size. In parallel, emerging applications including Internet-of-Things (IoT) and big data applications present high demands in terms of storage and computing capability, combined with challenging constraints in terms of size, power consumption and response latency. In this scenario, memristive devices have become promising candidates to complement the CMOS technology due to their CMOS manufacturing process compatibility, great scalability and high density, zero standby power consumption and their capacity to implement high density memories as well as new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause unique faulty behaviors that are not seen in CMOS, increasing significantly the complexity of test procedures. This paper provides a review about the manufacturing process of memristives devices, focusing on Valence Change Mechanism (VCM)-based memristive devices, and a comparative analysis of the CMOS and memristive device manufacturing processes. Moreover, this paper identifies possible manufacturing failure mechanisms that may affect these novel devices, completing the list of the already known mechanisms, and provides a discussion about possible faulty behaviors. Note that the identification of these mechanisms provides insights regarding the possible memristive devices’ defective behaviors, enabling to derive more accurate fault models and consequently, more suitable test procedures.

Memristive devices can be exploited for memory as well as logic operation paving the way for non von-Neumann Computation-In-Memory architectures. To validate the potential of such architectures accurate compact models for the memristive devices are required. As a standard device is not available, evaluating the performance of such an architecture is ambiguous. This paper proposes a flexible model for bipolar, filamentary switching, redox-based memristive devices. The model does catch both the device resistance ratio as well as the nonlinearity of the switching kinetics. It is used to perform design exploration for three memristive based circuit design (IMPLY, MAGIC and CRS) for computation-in-memory architectures.

Developing highly accurate and predictive models of redox-based memristive devices is highly important to enable future memory and logic design. As the switching mechanism is not known in all details yet, accurate device modeling is quite challenging. Here, we introduce six evaluation criteria for modeling filamentary switching devices based on the valence change mechanism, which is a subclass of redox-based memristive devices. The criteria include the plausibility of the simulated I-V and I-t characteristics, the nonlinearity of the switching kinetics, the feasibility of predicting complementary resistive switching correctly, the possibility of programming different resistance states, the state-dependence of the resistive switching, and the occurrence of a fading memory behavior. Four different models that have been proposed in literature are analyzed with respect to these criteria. These models are Kvatinsky's VTEAM model, the Stanford RRAM model, Strachan's TaOx memristor model and a nonlinear physics-based model proposed by our group.

Low operating voltage, high storage density, non-volatile storage capabilities, and relative low access latencies have popularized memristive devices as storage devices. Memristors can be ideally used for in-memory computing in the form of hybrid CMOS nano-crossbar arrays. In-memory serial adders have been theoretically and experimentally proven for crossbar arrays. To harness the parallelism of memristive arrays, parallel-prefix adders can be effective. In this work, a novel mapping scheme for in-memory Kogge-Stone adder has been presented. The number of cycles increases logarithmically with the bit width N of the operands, i.e., O ( log 2 N ), and the device count is 5 N . We verify the correctness of the proposed scheme by means of TaO × device model-based memristive simulations. We compare the proposed scheme with other proposed schemes in terms of number of cycle and number of devices.

Redox-based resistive switching devices are an emerging class of non-volatile ultra-scalable memory and logic devices. These devices offer complex internal device physics leading to rich dynamical behavior. Memristive device models are intended to reproduce the underlying redox-based resistive switching device behavior accurately to enable proper circuit simulations. A specific feature of resistively switching devices is the controllability of multi-level resistive states by using a current compliance during the SET operation. Here, we consider a one-transistor-one-resistive-switch circuit to study the multi-level capability of three different types of memristive models. The feasibility of current compliance induced multi-level resistance state control is a check for the accuracy of the memristive device model.

Memristive devices enable non-volatile data storage and in-memory computing capabilities. By using stateful logic approaches, hybrid CMOS nano-crossbar arrays offer additional functionalities such as arithmetic operations. To enable storage and computing on large-scale arrays, parasitic current paths within the array must be avoided. Therefore, for example, a complementary resistive switch (1CRS) or a bipolar rectifying element (‘selector’) in series to a resistive switching device (1S1R) is required at each cross-point junction to suppress low-ohmic sneak paths. In this work 1S1R arrays are considered. First, the in-memory adder concept, initially developed for CRS arrays, is adjusted for a 1S1R array. After that an optimized design is presented and verified by means of memristive simulations. Third, the energy consumption of both concepts is evaluated as a function of array size, and the delay of memristive adder designs are compared quantitatively.

Redox-based resistive switching devices are a potential candidate for future non-volatile memory. One type of these devices is the electrochemical metallization memory cell (ECM). To enable circuit design using resistive switching devices predictive simulation models are required. This work presents a physical model for the resistive switching in ECM cells that is based on the electrochemical driven growth and dissolution of a metallic filament. The simulation model covers self-consistently the basic experimental characteristics: I-V characteristics, nonlinear switching kinetics, and multilevel switching behavior. Furthermore, the RESET mechanism is discussed with respect to different ON states, i.e. galvanic contact versus tunneling gap.

Highly predictive memristive models of resistive switches are required to simulate the behavior of anti-serially connected resistive switches, so called complementary resistive switches (CRSs). As an emerging non-volatile device suited for ultra-dense memory architectures, CRS cells offer great potential also as content addressable memories. Here, we introduce a circuit model for TaOx-based resistive switches which we implemented in VerilogA. This model is capable of predicting CRS behavior correctly.

Recent advancements in resistive switching cell are based on three conduction mechanisms - electrochemical (ECM), Valence-change (VCM) and thermo-chemical (TCM). In the ECM type cells, migration of anions, typically oxygen ions, towards the anode, and reduction of the cation sublattice provide either metallically or semiconducting phases and triggers a bipolar memory operation. The major factors determining the functionality of the ECM cells are the electrode reaction and the transport kinetics. The VCM type switching is generally observed in metal oxides. Finally, the resistive switching based on the TCM mechanism is discussed. Whenever, this thermo-chemical effect dominates over the electrochemical effect, a unipolar switching behavior is observed. Conductive filament formed during the electroforming process is interpreted as a sequence of threshold switching and subsequent Joule heating, which triggers local redox reactions.

Many memory candidates based on beyond complementary metal-oxide-semiconductor (CMOS) nanoelectronics have been proposed, but no clear successor has yet been identified. In this paper, we offer a methodology for system-level analysis and address the relationship of the maximum performance of a given memory device type to device physics. The method is illustrated for the classical dynamic RAM (DRAM) device and for the emerging memory device known as the resistive RAM (ReRAM).