Yongjia Li

dblp:119/4126 · DBLP profile ↗
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6ranked-venue papers
2as first author
5since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 2 first-author · 4 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021
YearPublicationVenuePosition
2026 A 2 MHz Bandwidth Area-Efficient Multipath Hall Sensor With a Residual Ripple of 4.1 μT
abstract
This paper presents a multipath wide-bandwidth magnetic current sensor based on Hall effect. To simultaneously achieve wide bandwidth, minimal ripple and small area, the system incorporates a non-spun filter-free main path with offset elimination through a continuous-time compact auxiliary path. The auxiliary path cancels the main path offset via feedforward, alleviating the need for area-consuming blocking capacitor or DC servo loop. Therefore, the chip occupies only 1.52 mm2. To suppress ripple in the auxiliary path induced by spinning current, a ping-pong switch-capacitor (PPSC) filter is proposed which mitigates ripple by sampling and averaging in the forward path, with the system achieving a residual ripple of$4.1~{\mu }$T. Compared with the state-of-the-art Hall sensor, it achieves$5{\times }$bandwidth improvement,$2{\times }$ripple reduction while occupying$5{\times }$less area.
Yongjia Li, Jianlin Xia, Zhongyuan Fang, Feng Lin 0001, Encheng Zhu, Weifeng Sun 0001
IEEE Trans. Circuits Syst. I Regul. Pap.1
2025 A 870 ppm/V 53 ppm/ ° C 7 MHz Non-Trimmed RC Relaxation Oscillator Using Mixed-Signal Compensation Loop From - 40 ∘C to 165 ∘C
abstract
In this paper, an RC relaxation oscillator exhibiting robust performance over an extended temperature and supply range is proposed. By incorporating a digitally-assisted calibration loop, the design eliminates the errors from switch on-resistance, comparator offset and propagation delay. Fabricated using a 180 nm bipolar-CMOS-DMOS (BCD) process technology, the oscillator operates at a frequency of 7MHz with the supply sensitivity of 870 ppm/V across a voltage range of 1.7 to 4.2 V. The evaluation of 40 untrimmed samples achieved an average temperature coefficient (TC) of 52 ppm/$^{\circ}$C from$-$40$^{\circ}$C to 165$^{\circ}$C, with the worst observed TC being 81 ppm/$^{\circ}$C. The aging test results indicate small deviations of 0.3% and 11% in the oscillation frequency and its TC, respectively. Furthermore, the direct power injection test confirms its reliability and robustness with a maximum error of oscillation frequency of 6.4%.
Jianlin Xia, Yongjia Li, Weiyue Qu, Zhongyuan Fang, Jin Wu 0004, Feng Lin 0001, Encheng Zhu, Weifeng Sun 0001
IEEE Trans. Circuits Syst. I Regul. Pap.2
2025 A 50-kHz BW, 84.6-dB SNDR Noise-Shaping SAR ADC With Capacitor-Mismatch-Error-Free Switching Scheme
Yongjia Li, Jianhui Wu 0001
IEEE Trans. Very Large Scale Integr. Syst.2
2024 A Non-trimmed, 7 MHz and 52 ppm/°C Relaxation Oscillator with Loop Errors Compensation from -40°C to 165°C
abstract
This paper presents a RC relaxation oscillator with wide temperature range for automotive application. By using a digitally assisted calibration loop, the comparator offset and the loop delay are efficiently cancelled. With both reference voltage and current derived from the same ΔVBE-based bias circuit, the proposed design cancels leakage currents and makes the design insensitive to high-temperature. The oscillator was fabricated in a 180 nm BCD process, the oscillator operates at 7MHz and achieves a supply sensitivity of 870 ppm/V from 1.7 to 4.2 V at room temperature. Measurements on 40 samples without trimming show that it has an average temperature coefficient of 52 ppm/°C over a wide temperature range (-40°C to 165°C), with the worst case temperature coefficient of 65 ppm/°C.
Jianlin Xia, Yongjia Li, Zhongyuan Fang, Jin Wu 0004, Feng Lin 0001, Weifeng Sun 0001
ISCAS2
2021 Neural network's selection of color in UI design of social software
Yongjia Li, Maeng Hyung Jae
Neural Comput. Appl.2
2012 A continuous-time level-crossing ADC with 1-bit DAC and 3-input comparator
abstract
A novel continuous-time level-crossing analog-to-digital converter (LC-ADC) for biomedical application is proposed. Lower power consumption and less design complexity with respect to the conventional designs are achieved due to 1) replacing the n-bit digital-to-analog converter (DAC) with a 1-bit DAC; 2) introducing a 3-input comparator and switching off the idle branches in the following stages when possible; 3) utilizing the opposite polarity of the differential input signals and fixing the comparison window with only one reference level; 4) splitting the level-crossing detections. Designed to be implemented in 0.18 µm CMOS technology, the proposed ADC achieves 8 bits of resolution with much lower power consumption than conventional LC-ADCs.
Yongjia Li, Wouter A. Serdijn
ISCAS1