EDBT 2026 Demo / reviewers in the wild / expert
Yasuhiro Takei
dblp:119/4202
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2017
0000-0003-1279-5608ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
High-performance computing · 56% GPUs and heterogeneous computing · 44% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing › heterogeneous programming models
OpenCL |
0.3 | 1 | 2017 | OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology · IEEE Trans. Parallel Distributed Syst. 2017 |
High-performance computing
stencil computation |
0.3 | 1 | 2017 | OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology · IEEE Trans. Parallel Distributed Syst. 2017 |
High-performance computing
scientific computing |
0.1 | 1 | 2017 | OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology · IEEE Trans. Parallel Distributed Syst. 2017 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization MethodologyabstractStencil computation is widely used in scientific computations and many accelerators based on multicore CPUs and GPUs have been proposed. Stencil computation has a small operational intensity so that a large external memory bandwidth is usually required for high performance. FPGAs have the potential to solve this problem by utilizing large internal memory efficiently. However, a very large design, testing and debugging time is required to implement an FPGA architecture successfully. To solve this problem, we propose an FPGA-platform using C-like programming language called open computing language (OpenCL). We also propose an optimization methodology to find the optimal architecture for a given application using the proposed FPFA-platform. According to the experimental results, we achieved 119 - 237 Gflop/s of processing power and higher processing speed compared to conventional GPU and multicore CPU implementations. Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Shunsuke Tatsumi, Masanori Hariyama |
IEEE Trans. Parallel Distributed Syst. | 2 |
| 2012 | FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom acceleratorsabstractHeterogeneous multi-core architecture with CPUs and accelerators attract many attentions since they can achieve power-efficient computing in various areas from low-power embedded processing to high-performance computing. Since the optimal architecture is different from application to applications, it is important to explore suitable architectures for different applications. In this paper, we propose an FPGA-based heterogeneous multi-core platform with custom accelerators for power-efficient computing. Our platform allows to select the most suitable accelerator according to the requirements of an application. Moreover, we optimize the number of ALUs, memory and interconnection network of the selected accelerators to increase the performance and to reduce the power consumption. Experimental results with simple media processing applications times power-efficient compared to the GPU. Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama |
ISCAS | 2 |