Deep spiking neural networks (SNNs) have shown remarkable progress due to improvements, such as training algorithms. However, most of them have not considered the features of neuromorphic devices. Their improvement has relied on soft resets, which are computationally expensive and unsuitable for neuromorphic devices. To address this, this paper proposes gradient clipping in hard reset-based deep SNNs and explores how device noise enhances learning performance. According to our experiments on various datasets and models, the proposed approach improved the training performance of deep SNNs with hard reset. These findings bridge gaps between SNN algorithms and hardware constraints, paving the way for efficient neuromorphic computing.

Recently, many large-scale neuromorphic systems that emulate spiking neural networks have been presented. Biological evidence emphasizes the importance of the log-normal distribution of biological neural and synaptic parameters in the brain; however, this fact is easily ignored sometimes, and the parameters are excessively optimized to scale up a system. This is because high-precision parameters require floating-point arithmetic–an operation known to consume high-energy and result in a high implementation cost in digital hardware. In this study, we propose a novel neuron implementation model that enhances neural and synaptic dynamics using the time-embedded floating-point arithmetic for better biological plausibility and low-power consumption. The proposed algorithm enables sharing temporal information with a membrane potential by time-embedded floating-point arithmetic, thus minimizing the memory usage of the neural state. In addition, this method need not access the static random-access memory at every time step, thus reducing the dynamic power consumption, even with a floating-point precision neural and synaptic dynamics. Using the proposed model, we implemented a core group with a total of 8,192 neurons on a field-programmable gate array device, Xilinx XC7K160T. The core group is designed for use in large-scale neuromorphic systems. We tested the neuron model in a core under various experimental conditions.

This paper proposes a new clock offset estimation that mitigates unwanted link asymmetry for precise clock synchronization. The main contribution is to address the primary and traditional design issue of the IEEE 1588 standard precision time protocol (PTP), which estimates clock offset under the assumption that the delays of exchanged packets are symmetric. To mitigate the issue, we focus on the fact that PTP measures asymmetry variation through the derivatives of its timestamps with respect to the time step. By exploiting the measurement of the variation, the proposed approach defines the asymmetry in the form of a linear differential equation (LDE) and leverages the LDE to define and exclude asymmetry-induced errors. Additionally, we clearly derive the state transition of the asymmetry. Subsequently, we derive a novel state-space model from our approach. The model describes PTP clock offset estimation perfectly, allowing optimal clock offset estimation. We verify the theoretical validity of the proposed method with real data. Our approach improves PTP accuracy by more than thousand times and achieves an accuracy at the level of tens to hundreds of nanoseconds on an asymmetric communication link. Our approach realizes an accuracy comparable to that of PTPv2, without the cost of specialized hardware.

An asynchronous continuous-time level-crossing analog-to-digital converter (LC-ADC) for high-throughput, high-resolution applications is presented. The proposed 10-bit ADC architecture comprises two stages of level-crossing ADCs, the first stage resolving for 5 MSBs and the second folded residue stage for 5 LSBs. Gray encoding of the output bits ensure single-bit transitions between adjacent digital outputs. Compared to uniform-sampling synchronous ADCs, LC-ADCs generate fewer samples for sparse signals, useful in many applications for biomedical signal acquisition, event-driven computer vision, etc. Unlike conventional LC-ADCs with a few comparators tuned for lower power consumption to acquire sparse signals, this two-tier LC-ADC is optimized for high-resolution tracking of continuous signals, like Electrocardiogram (ECG). Designed and fabricated in 0.18-μm CMOS technology, chip area of the proposed ADC is 1310 × 125 μm2. Operating at 1.8 V supply, the ADC consumes 160-426 μW for 1 Hz to 200 kHz input frequencies at full scale amplitude and achieves an energy efficiency figure-of-merit of 4.16-pJ/conv.

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at $3.6\times 10^{7}$ synaptic events per second per 16k-neuron node in the hierarchy.

This paper presents a new DVS sensor with one order of magnitude improved contrast sensitivity over previous reported DVSs. This sensor has been applied to a bio-inspired event-based binocular system that performs 3D event-driven reconstruction of a scene. Events from two DVS sensors are matched by using precise timing information of their ocurrence. To improve matching reliability, satisfaction of epipolar geometry constraint is required, and simultaneously available information on the orientation is used as an additional matching constraint.

Recent advances in neuromorphic engineering for brain-like computing and neural prostheses are converging towards realization of electronic synaptic arrays approaching the integration density and energy efficiency of the human brain. A major impediment in this development is the real-time synaptic routing in a large-scale spiking neuron architecture. Here we present a hierarchical address-event routing (HiAER) communication architecture for routing neural events in a scaleable reconfigurable large-scale neuromorphic system. The neural events are routed in real-time through synaptic connections with configurable parameters governing connectivity, synaptic strength, and axonal delay. The HiAER architecture is implemented on a hardware platform with five Xilinx Spartan-6 FPGA cores.