Massive MIMO systems are promising for wireless communications beyond 5G, but scalable Direction-of-Arrival (DOA) estimation in these systems is challenging due to the increasing number of required antennas. Existing solutions, model-based or data-driven (typically using neural networks), face scalability issues with the growing antenna array size. To address this issue, we propose a hybrid system that makes the overall approach scalable. In the front-end, we employ a modular distributed approach namely, the method of sparse linear inverse to compute a proxy spectrum from the sampled covariance matrix of the antenna subarrays. The proxy drives a fixed lightweight back-end which consists of a 1-dimensional Convolution Neural Network (1D-CNN) and a simplified peak extraction. The input proxy dimension being independent of the antenna count makes the neural network input invariant of the array size, enabling it to handle multiple array sizes without requiring any modification of the neural network structure. To reduce the computation of the covariance matrix and proxy spectrum, we employ a system of subarrays with Nearest-Neighbor communication. The proposed approach was implemented on a Xilinx ZCU102 FPGA targeting 100 MHz frequency for 8 to 256-element arrays. We achieve below 1 ms processing time for an array of 256 antennas while requiring significantly less computation than both model-based and data-driven approaches for large antenna arrays.

This paper analyzes the phase tracking capability of a fractionally-spaced equalizer (FSE) to propose a dedicated equivalent model as a clock and data recovery (CDR) loop. In contrast to reported FSE studies, our study focuses on quantitative determinations for equivalent CDR loop parameters pertinent to practical CDR designs using FSE. By analyzing second-order statistics and eigenmodes for finite-impulse response (FIR) transversal filter-based FSE as a function of the entire sampling phases, we can estimate the bandwidth tied to the critical eigenmode and additive mean-squared error (MSE). This analysis can guarantee the worst-case behavior of the FSE as a CDR. The behavioral simulation results show the effectiveness of the proposed CDR model by demonstrating the error transfer function, jitter tolerance (JTOL), and bit-error-rate (BER). Based on the analysis, an enhanced decision scheme for the FSE-alternating technique is proposed. The behavioral simulation result shows a 38.5% reduction in the standard deviation of error compared to our previous work for an infinite-range plesiochronous system.

With the development of Radio Frequency (RF) massive Multiple Inputs-Multiple Outputs (MIMO) array systems for Beyond 5G (B5G) applications, real-time DOA estimation has become challenging due to large antenna architectures producing a staggering amount of data. Traditional DOA estimation techniques are not scalable since they either require multiple snapshots of data or computationally expensive matrix operations hindering fast processing. To address these challenges, we propose a single-snapshot DOA processor based on the Alternating Direction Method of Multipliers (ADMM). The algorithm is modified to handle complex-valued measurements. We develop a High-Level Synthesis (HLS) based scalable FPGA design to handle multiple array sizes ranging from 8 to 512 elements. Our system implemented on a Xilinx Ultra96-V2 FPGA, operates at a frequency of 100 MHz with a sub-200μs processing time for a 512-antenna array, thereby meeting the millisecond-level processing time specifications of B5G applications.

This paper presents a new time-based pipelined analog-to-digital converter (ADC) with multiplying-DAC (MDAC) stages capable of robust 2 × residue amplification by subtracting two pulse widths. First, the input voltage is converted into two timing pulses containing the information of the time difference between their rising edges. Each MDAC stage performs 1.5-bit quantization and generates two turn-on pulses with pulse widths bearing the opposite signs of the residue, + Tresand -Tres. The following pair of integrate-and-fire circuits, each containing a current source charging a capacitor to a threshold voltage, computes the difference between the two pulse widths, Tres-(-Tres)=2Tres, and generates new timing pulses bearing the 2× amplified residue for the next stage. The circuit non-idealities in the MDACs contribute to the offset errors but not to the gain errors in their transfer curves, making the calibration simple. Moreover, the ADC does not require amplifiers, making it suitable for low-voltage digital processes. The prototype 10-bit pipelined ADC fabricated in 28-nm CMOS dissipates 1.55-mW at 125-MS/s and occupies 0.025 mm2. With signal-to-noise and distortion ratio of 44.3 dB and spurious-free dynamic range of 53 dB for a 1-MHz sinusoidal input, the ADC has a figure of merit of 96.8-fJ/conversion step.

A model-first flow is demonstrated for designing and validating a high-speed serial receiver in a digital TV. Starting with a functional model of the top-level mixed-signal system rather than with transistor-level designs helps detect problems due to the increasing interaction between the analog and digital circuits. Once the functionality of the system model is verified, the model can be leveraged as the specification for generating and validating the circuit and physical implementations of the system, automating a large portion of the design process.