Intrusion event detection in distributed fiber optic sensing systems plays a vital role in urban emergency management and public safety. However, current AI-based systems face high false positive and false negative rates, as well as limited generalizability, due to variations in dataset quality, processing methods, and model architectures. To address these issues, we propose the Riemannian-Transformer-OTDR (RTO) model, an explainable deep-learning approach based on Riemannian manifolds. By exploiting the manifold space, our method identifies stable latent representations of dynamic data distributions from similar events, embedding intrusion detection within this latent manifold. The RTO model accurately identifies identical event types across diverse scenarios, reducing misclassification rates and enhancing model stability. Field tests using a distributed fiber optic sensing system validated the effectiveness of RTO: it achieved 98.43% accuracy in a subway construction scenario and demonstrated its cross-scenario generalization ability by maintaining 94.21% accuracy in gas pipeline monitoring, with 80.79% accuracy in a 100% noisy environment. Additionally, signal structure analysis of misclassified samples revealed insights into the model’s learning process. Our analysis of performance degradation across scenarios and noise levels further clarifies the RTO mechanisms and explainability. Ultimately, the RTO enables precise, retraining-free intrusion event classification across multiple scenarios, offering a practical solution for rapid event detection deployment in various domains.

The key features of 5G network (i.e., high bandwidth, low latency, and high concurrency) along with the capability of supporting big data platforms with high mobility make it valuable in coping with emerging medical needs, such as COVID-19 and future healthcare challenges. However, enforcing the security aspect of a 5G-based smart healthcare system that hosts critical data and services is becoming more urgent and critical. Passive security mechanisms (e.g., data encryption and isolation) used in legacy medical platforms cannot provide sufficient protection for a healthcare system that is deployed in a distributed manner and fail to meet the need for data/service sharing across "cloud-edge-terminal" in the 5G era. In this article, we propose a security awareness and protection system that leverages zero-trust architecture for a 5G-based smart medical platform. Driven by the four key dimensions of 5G smart healthcare including "subject" (i.e., users, terminals, and applications), "object" (i.e., data, platforms, and services), "behavior," and "environment," our system constructs trustable dynamic access control models and achieves real-time network security situational awareness, continuous identity authentication, analysis of access behavior, and fine-grained access control. The proposed security system is implemented and tested thoroughly at industrial-grade, which proves that it satisfies the needs of active defense and end-to-end security enforcement of data, users, and services involved in a 5G-based smart medical system.

Post-silicon validation is concerned for discovering design errors that escape to the silicon prototypes. Recent research efforts have shown how to reuse the constraints from pre-silicon verification to support post-silicon constrained-random validation. The objective is to subject the prototype to a large volume of random, yet functionally-compliant stimuli. In this paper, we present a new method that facilitates on-chip stimuli generation compliant to constraints with weighted distributions.

The constrained-random methodology is widely used during the pre-silicon verification of very-large scale integrated circuits. Recently, research efforts have been made to support the application of constrained-random patterns during the post-silicon validation stage. In this paper, we present a new method, including both software algorithms and on-chip hardware structures, for in-system constrained-random generation of stimuli sequences that are uniformly distributed. More specifically, we facilitate in-system application of constrained-random sequences that are cyclic-random, i.e., all the valid values from the user-constrained space are generated only once before the entire sample space is exhausted. While software simulation environments commonly support this feature, e.g., randc in SystemVerilog, to the best of our knowledge this is the first time it is shown how such feature can be ported to hardware environments.

Post-silicon validation is critical for exposing subtle design errors that have escaped to the silicon prototypes. Its effectiveness is conditioned by in-system application of a large volume of functionally-compliant stimuli. In this paper, we present a methodology to design constrained-random stimuli generators, which are placed on-chip and are configurable at design-time to generate in-system functionally-compliant stimuli subject to user-programmable constraints provided at validation time. Central to our method is a cube-based representation of constraints. These cubes are used as masks that force pseudo-random sequences to map onto functionally-compliant stimuli. To reduce the on-chip storage requirements, masks are compressed at design-time and expanded on-the-fly at validation time using decompression circuitry. Experimental results evaluate the impact of our method on the requirements for on-chip logic and memory resources.

Post-silicon validation is becoming widely adopted because it runs significantly faster than pre-silicon verification and hence it helps uncover subtle design errors that escape to silicon prototypes. However, it is hindered by limited controllability and observability, which makes it challenging to reuse pre-silicon content. In order to enable the reuse of stimuli constraints from pre-silicon verification environments, we present a method that facilitates the on-chip generation of uniformly distributed constrained-random stimuli. More specifically, our method, which relies on new pre-processing steps and on-chip hardware features, can generate in real-time pseudo cyclic-random stimuli with no repetition until the space of the compliant stimuli is exhausted.

Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the existing work for on-chip generation of functionally-compliant randomized sequences with support for sequential constraints.

During post-silicon validation a large number of constrained random stimuli are applied to expose the subtle design errors that have escaped to the silicon prototypes. In this paper we present a new method to design constrained random stimuli generators, which are programmable and can be placed on-chip to generate extensive random, yet functionally-compliant, sequences for real-time/in-system validation. The basic idea is to translate the constraints for constrained-random variables into binary cubes, whose specified values are used as masks to correct random sequences. To reduce the volume of data needed to be placed on-chip, the cubes are efficiently encoded and expanded in real-time. Experimental results confirm the effectiveness of this new method when compared against the prior work on the topic.

A fast-lock-in harmonic-free all-digital delay-locked-loop (ADDLL) in STMicro 32nm CMOS technology is presented. The ADDLL uses a novel complementary delay line with lattice-type delay elements. The complementary line can effectively reduce at most 50% active delay elements than a single line. Less active delay elements make better suppression of supply-induced jitter. The lattice-type delay element is beneficial to high frequency applications because of its small intrinsic delay. The ADDLL employs a 9-bit configurable SAR controller to achieve fast lock. Moreover, it can work in a wide-range application (200MHz ∼ 2GHz) without the harmonic-lock problem of conventional SAR controllers. Under a 1.1V power supply, the ADDLL has a delay resolution of 8 ps and the lock time is 36 cycles at 200 MHz and 24 cycles at 2GHz.