As conventional computers based on von Neumann architecture approach their physical and performance limits, unconventional computing paradigms such as Cellular Neural Networks (CellNNs) have emerged as promising platforms for real-time, massively parallel analog computation. However, conventional analog CellNNs suffer from scalability and power constraints due to large cell hardware overhead. This work investigates the integration of memristor-based crossbar arrays into CellNN architectures to address these limitations by exploiting their analog tunability, high density, and low power operation. A 1-Transistor-1-Memristor (1T1R) crossbar is proposed for implementing the coupling weights defining the CellNN gene. Device nonlinearity, asymmetry and stochastic variability are incorporated using the physics-based JART VCM memristor model, enabling accurate mapping of target weights onto memristor conductances through numerical optimization and differential-pair encoding. Simulations of edge detection tasks confirm high functional accuracy and robustness, while Monte Carlo analysis reveals variability’s impact, underscoring the need for variability-aware design of reliable memristor-CNN hardware.

Memristive devices are promising enablers for computing-in-memory architectures, offering reduced latency and energy consumption compared to conventional designs. Among these, the memristive device-based Cellular Nonlinear Network (M-CNN) provides a compact framework for universal computing, including image processing and neuromorphic computing. In this work, we investigate the use of IGZO-based devices exhibiting gradual switching as core elements of M-CNN cells. A simulation approach based on measured I-V-characteristics is developed to evaluate device–circuit interactions. We first analyze the limitations of the conventional M-CNN cell core, where asymmetric I-V-characteristics restrict voltage levels and accelerate device degradation. To address these issues, we propose a symmetrized cell that mitigates asymmetry, intrinsically limits cell voltage, and supports differential readout. The results demonstrate that gradual switching enables reliable distinction of input current levels while ensuring stable operation and reduced power consumption, thus paving the way for robust IGZO-based M-CNN implementations.

Advancements in emerging technologies have recently increased the traction of non-von Neumann design styles. One of the most popular design styles in this domain involves using memristors to perform logic operations in memory, known as Logic-in-Memory (LiM). Memristor Aided Logic (MAGIC) is one of such LiM based design style that is widely used given its benefits in latency and energy. Several prior works have focused on the generation of logic operations, also called microoperations, for LiM based on the MAGIC design style. Recently, the generation of SPICE netlists for MAGIC design style has been achieved by the MemSPICE tool. While this represents a significant step forward, verifying the correctness of the generated netlists still depends on SPICE-level simulations. These simulations become particularly impractical for medium-to-large designs presenting a bottleneck in the validation process. To address this limitation, in this paper, we introduce veriSiM, an automated formal verification methodology for MAGIC-based LiM. More concretely, it ensures the correctness of the generated LiM SPICE netlists against the golden reference Verilog design. Our methodology involves generating clauses from the SPICE netlists and verifying them against clauses generated from the golden reference Verilog design, using the high-performance Z3 solver to perform the equivalence checking. The clause generation process from the SPICE netlists needs to be based on several conditions, which have been identified and discussed in detail. We have used several benchmarks from ISCAS’85, ISCAS’89, and ITC’99 to demonstrate the efficacy of the veri

Resistive random-access memory (RRAM)-based computation-in-memory (CIM) architectures offer a promising solution to meet the stringent energy efficiency demands of executing artificial intelligence (AI) algorithms directly on edge devices. However, these architectures suffer from the read-disturb problem, which can lead to accumulated computational errors over time. To maintain the required level of computational accuracy, conventional approaches rely on a static reprogramming process after a predefined number of read cycles, necessitating large counters and resulting in inefficiencies. This paper presents experimental results using real RRAM devices to analyze the read-disturb effect and builds on these insights to propose a circuit-level detection methodology for real-time monitoring of conductance drifts. The proposed method initiates reprogramming only when the device drift exceeds a defined threshold and reprogramming is actually needed. Additionally, an analytical method is developed to determine the minimum conductance state ratio needed to meet reliable detection criteria. Based on this foundation, the proposed detection technique is further optimized for dynamic identification of read-disturb effects. Experiment-augmented SPICE simulation results, using a calibrated model implemented in TSMC 40 nm CMOS technology, validate the functionality and effectiveness of the proposed detection approach. These results demonstrate its potential to improve both the reliability and efficiency of RRAM-based CIM architectures that provide up to a 4x improvement in energy-efficiency compared to traditional periodic reprogramming methods.

Realized memristors exhibit a unique phenomenon called the fading memory effect, where the memristor response to an AC signal is determined by its characteristics (waveform, amplitude, frequency, and DC offset) rather than the memristor initial conditions. Recently, a method for programming Hewlett Packard’s TaOxmemristor to a target state was proposed, involving configuring the DC offset of a high-frequency square-wave AC voltage input. This served as a basic application example that exploits fading memory in non-volatile memristors, but didn’t consider non-ideal effects. Here, we assess the method applicability in a HfOx-based VCM resistive switch from Forschungszentrum Julich incorporating a variability-aware physics-based model.

We have successfully fabricated one of the earliest array-scale prototypes of a Memristive Cellular Nonlinear Network (M-CNN) with interconnected cells. In this live demonstration, we will showcase the operation of this 4x4 M-CNN array performing an edge detection task according to our previous work [1]. A user-defined input will be applied to the network, and the computing results will be visualized alongside the simulated operation of a standard CNN for comparison.

Emerging non-volatile memories (eNVM) promise to solve the imminent von Neumann bottleneck by enabling future computing systems to utilize the computing-in-memory (CIM) paradigm offering exceptional energy efficiency and performance advantages. As Moore's law becomes obsolete, CIM architectures are prominent candidates to push the boundaries of existing computing systems and usher in a new generation of computing models, such as neuromorphic systems. Furthermore, conventional systems face another significant problem in addition to the von Neumann bottleneck. Hardware security threats (e.g., Rowhammer) have gained momentum and can expose an entirely pristine attack surface for adversaries. These vulnerabilities distinguish themselves by being particularly challenging to patch because their origin lies in the rigid hardware layout. Unfortunately, neuromorphic systems are no exception. We presented NeuroHammer as one of the first unique hardware security attacks on eNVMs, enabling an attacker to intentionally flip bits in memristive crossbar arrays. This article extends our previous results by thoroughly examining the underlying concepts leading to the NeuroHammer attack. First, we investigate memory access patterns to gain insight into the tangible impact of NeuroHammer. Second, we extend our simulation methodology to accommodate transistor/one resistive (1T1R) crossbar structures and prove the prevalence of the NeuroHammer attack. Finally, we discuss the real-world implications of NeuroHammer on CIM architectures.

Existing logic-in-memory (LiM) research is limited to generating mappings and micro-operations. In this paper, we present MemSPICE, a novel framework that addresses this gap by automatically generating both the netlist and testbench needed to evaluate the LiM on a memristive crossbar. MemSPICE goes beyond conventional approaches by providing energy estimation scripts to calculate the precise energy consumption of the testbench at the SPICE level. We propose an automated framework that utilizes the mapping obtained from the SIMPLER tool to perform accurate energy estimation through SPICE simulations. To the best of our knowledge, no existing framework is capable of generating a SPICE netlist from a hardware description language. By offering a comprehensive solution for SPICE-based netlist generation, testbench creation, and accurate energy estimation, MemSPICE empowers researchers and engineers working on memristor-based LiM to enhance their understanding and optimization of energy usage in these systems. Finally, we tested the circuits from the ISCAS’85 benchmark on MemSPICE and conducted a detailed energy analysis.

In-Memory Computing (IMC) introduces a new paradigm of computation that offers high efficiency in terms of latency and power consumption for AI accelerators. However, the non-idealities and defects of emerging technologies used in advanced IMC can severely degrade the accuracy of inferred Neural Networks (NN) and lead to malfunctions in safety-critical applications. In this paper, we investigate an architectural-level mitigation technique based on the coordinated action of multiple checksum codes, to detect and correct errors at run-time. This implementation demonstrates higher efficiency in recovering accuracy across different AI algorithms and technologies compared to more traditional methods such as Triple Modular Redundancy (TMR). The results show that several configurations of our implementation recover more than 91% of the original accuracy with less than half of the area required by TMR and less than 40% of latency overhead.

In-memory computing (IMC) has gained signifi- cant attention recently as it attempts to reduce the impact of memory bottlenecks. Numerous schemes for digital IMC are presented in the literature, focusing on logic operations. Often, an application's description has data dependencies that must be resolved. Contemporary IMC architectures perform read followed by write operations for this purpose, which results in performance and energy penalties. To solve this fundamental problem, this paper presents in-memory mirroring (IMM). IMM eliminates the need for read and write-back steps, thus avoiding energy and performance penalties. Instead, we perform data movement within memory, involving row-wise and column-wise data transfers. Additionally, the IMM scheme enables parallel cloning of entire row (word) with a complexity of O(1). Moreover, we analyzed the energy consumption of the proposed technique on an RRAM crossbar with an experimentally validated JART VCM v1b model. The IMM increases energy efficiency and shows 2x performance improvement compared to conventional data movement methods.

In this paper, the design of an isolated Memristor Cellular Nonlinear Network (CNN) cell with discrete electronic elements is presented. The proposed versatile circuit allows for adjustable cell dynamical characteristics, controlled by design parameters, while the discrete element approach enables simple on-board implementation without the need for large-scale integration, which is necessary for testing hardware with individual fabricated memristors. A voltage-mode approach, that makes use of the diversity of operational amplifiers, is preferred here over a current-mode one that necessitates a large number of individual transistors. The dynamical properties of the system are initially investigated through the calculation of equilibrium points and further illustrated applying the concept of State Dynamic Routes (SDRs) for the cell assuming that the memristor dynamics are much slower than the capacitor voltage dynamics. Moreover, the effect of design parameters on the cell dynamics is being investigated, showing how the scaling of the operating voltage, as well as a plethora of CNN variants -i.e., the Chua-Yang and Full Range models-, can be implemented within the same design. Finally, the nonlinear conductance properties of real memristor devices are incorporated into the study, demonstrating interesting bifurcation phenomena between the cell monostability and bistability for specific parameter values.

Physical Unclonable Functions (PUFs) offer the natural advantage of built-in key generation, thus eliminating the costly process of embedding unique key after manufacturing millions of integrated circuits. When PUFs are deployed for the application, all the Challenge-Response Pairs (CRP) are collected and stored in a trusted server, and the responses are compared with the one from the device during the run-time - forming the crux of various security protocols. Two issues are commonly faced during PUF designs. First, to enhance the applicability of PUF, larger set of CRP is desirable, which is referred to as a strong PUF. Second, due to the emergence of machine learning-based PUF modelling attacks, it is now imperative to have a PUF demonstrating resistance against such attacks. In this paper, we propose a novel Parity Resistive RAM PUF (PR-PUF) implemented using RRAM crossbar architecture. PR-PUF supports low-overhead reconfiguration, where both the original and reconfigured CRP space enhances the CRP size, with average uniqueness between reconfiguration of 49.98%. The construction also demonstrates excellent robustness against various modeling attacks. We present detailed design analysis and circuit-level simulation studies.

For reproducible resistive switching in memristive devices, electroforming is a crucial process. However, a deeper understanding of the electroforming process is still lacking due to unavailability of a proper simulation tool. Here, we propose a physics-based compact model for the electroforming of valence change mechanism (VCM) memristive devices. The developed JART VCM Forming model is experimentally validated with the ZrOx-based memristive device. Furthermore, the electroforming process in different 1T1R memristive arrays is simulated with this model. The study shows that the electrical characteristics of each device in the array after the forming process are influenced by word/bit line series resistance. In addition, control effects depending on the channel width and applied gate voltage of transistor in the 1T1R cell are also investigated with the compact model simulation.

The field of neuromorphic computing is approaching an era of rapid adoption driven by the urgent need of a substitute for the von Neumann computing architecture. NEUROTEC I: “Neuro-inspired Artificial Intelligence Technologies for the Elec-tronics of the Future” project is an initiative sponsored by the German Federal Ministry of Education and Research (BMBF for its initials in German), that aims to effectively advance the foundations for the utilization and exploitation of neuromorphic computing. NEUROTEC I stands at its successful “final stage” driven by the collaboration from more than 8 institutes from the Jiilich Research Center and the RWTH Aachen University, as well as collaboration from several high-tech industry partners. The NEUROTEC I project considers the field interplay among materials, circuits, design and simulation tools. This paper provides an overview of the project's overall structure and discusses the scientific achievements of its individual activities.

Emerging non-volatile memory (NVM) technologies offer unique advantages in energy efficiency, latency, and features such as computing-in-memory. Consequently, emerging NVM technologies are considered an ideal substrate for computation and storage in future-generation neuromorphic platforms. These technologies need to be evaluated for fundamental reliability and security issues. In this paper, we present NeuroHammer, a security threat in ReRAM crossbars caused by thermal crosstalk between memory cells. We demonstrate that bit-flips can be deliberately induced in ReRAM devices in a crossbar by systematically writing adjacent memory cells. A simulation flow is developed to evaluate NeuroHammer and the impact of physical parameters on the effectiveness of the attack. Finally, we discuss the security implications in the context of possible attack scenarios.

As the cost of keeping Moore’s law alive is ever increasing, unconventional device and circuit concepts are being explored, both in industry and in academic research arena. Among the new devices being explored are two terminals redox-based memristive devices, which can function as both a nonvolatile memory and a computing element. For enabling Computation-in-Memory (CIM) concepts, these devices are generally integrated in a passive configuration or in an active configuration, where transistors are employed together with the memristive switches. However, the reliability and variability of the memristive devices might impact the performance of CIM circuits. In this work, we experimentally demonstrate the impact of device-to-device (D2D) and cycle-to-cycle (C2C) variability on a simple IMPLY logic gate realized in passive and active configurations. The experimental data is theoretically verified by a physics based Verilog-A model of the memristive devices. Our findings suggest that the success rate of the logic operation can be increased by exploiting the D2D variability in the memristive devices.

Cellular Nonlinear Networks (CNN) as a powerful paradigm is highly suitable for signal processing of multiple tasks, since they can execute cascaded processing operations in a one-layer array via real-time template updating. Their VLSI implementation by using the conventional CMOS-based integration technology, however, remains a big challenge. The memristive CNN (M-CNN) offers several merits over conventional CNN, such as compactness, nonvolatility, versatility. This paper presents a direct comparison of computing performance between the M-CNN and the conventional CNN for the implementation of a LOGAND operation template using circuit simulation. Our findings show that the M-CNN implementation offers rapid attainment of equilibrium state compared to the CNN implementation. In addition, the result is stored in a non-volatile manner in the M-CNN whereas the CNN only offers a volatile storage.

In the group of emerging non-volatile storage technologies, redox-based memristive devices stand out due to their possibility for extreme dense integration, low power consumption and multilevel capabilities. The opportunity to directly perform Boolean logic operations using memristive devices opens a promising path towards Computation-in-Memory. Recently 7- state memristive devices based on TaOx were used to realize a ternary adder circuit as well as a ternary Łukasiewicz logic and fuzzy logic. Logic that uses more than two truth values promises to reduce the number of devices that are needed for a certain operation and thereby further increases the integration density. In this work, we propose a multinary logic for three, five and seven truth values based on the Łukasiewicz logic and show the performance for the implication and negation operation. We, therefore, used the physics-based compact model JART VCM v1b to describe the relation between RESET voltage and high resistive state and then performed the logic operations.

In this work, TaOx based ReRAM devices were fabricated by reactive sputtering. The impact of RF power on the device characteristics was investigated using five different RF powers ranging from 116 W (RF 20%) to 356 W (RF 60%), resulting in different film deposition rates. Depending on RF power, both the initial device resistance (Rinitial) and forming voltage (Vform) were found to be changed. The switching layer sputtered at 116 W shows the highest Rinitial(80 GΩ), whereas the lowest resistance (50 kΩ) is obtained at 236 W. The device RESET level (Roff) is a function of Rinitialand Vform. The largest memory window (Roff/ Ron~ 105) and 2-bit MLC operation are achieved at 236 W deposition power. These devices show excellent retention at 125 °C for 104seconds and good endurance up to 106cycles. These results reflect the impact of the sputtering deposition power on the electrical performance of the ReRAM devices. It is due to the fact that the structural defects and oxygen content in the deposited film are modulated by the sputtering power.

A new architecture of charge-pump circuit is discussed that can be used to generate high positive and negative voltages to drive a common load (Load can be capacitive, resistive or both). Basic cell used for charge-pump consists of two phase clock signals, charge transfer NMOS transistors and bootstrapped configuration to boost the gate drive of NMOS transistors. Due to use of NMOS transistors, output resistance of circuit is lower than conventional circuits thus able to drive high load current. Electrical conditions of all devices used in the circuit is managed in such a way that there is no electrical stress across any transistor. Circuit is design and implemented in BCD-110nm technology using conventional (No DMOS) transistors.

Recent advancements in resistive switching cell are based on three conduction mechanisms - electrochemical (ECM), Valence-change (VCM) and thermo-chemical (TCM). In the ECM type cells, migration of anions, typically oxygen ions, towards the anode, and reduction of the cation sublattice provide either metallically or semiconducting phases and triggers a bipolar memory operation. The major factors determining the functionality of the ECM cells are the electrode reaction and the transport kinetics. The VCM type switching is generally observed in metal oxides. Finally, the resistive switching based on the TCM mechanism is discussed. Whenever, this thermo-chemical effect dominates over the electrochemical effect, a unipolar switching behavior is observed. Conductive filament formed during the electroforming process is interpreted as a sequence of threshold switching and subsequent Joule heating, which triggers local redox reactions.