This paper proposes a digital background calibration scheme for the compensation of the linear and the third-order nonlinear gain errors of the residue amplifier (RA) in pipelined ADCs. The proposed calibration method, called the piecewise multi-correlation estimation (PMCE) technique, injects two pseudo-random number (PN) sequences within two adjacent dither windows to extract gain coefficients. This method transforms the estimation of nonlinear gains into the estimation of two linear gains, thus achieving rapid convergence. The proposed calibration scheme does not result in the output swing degradation of the multiplying DAC (MDAC) due to dither injection. The required modification to analog circuits involves only three additional comparators and a capacitor for dither injection. Monte Carlo simulation results of a 14-bit 1.3GS/s pipelined ADC show that the average SFDR of the ADC is improved from 59.61 dB to 91.11 dB.

This paper presents a novel parallel convolution-self-attention neural network (PCSANN) based calibration scheme for Pipelined and Pipelined-SAR ADCs. Combining convolution neural network (CNN) and self-attention neural network (SANN), the proposed architecture jointly calibrates various nonlinearities in ADCs as a black box, including comparator offsets, inter-stage gain error (IGE), inter-stage nonlinearity, digital-to-analog converter (DAC) errors, memory effect (ME), etc. This proposed calibration scheme is validated with a fabricated 12-bit 150MSps pipelined ADC prototype and a fabricated 12-bit 750MSps pipelined-SAR ADC prototype. Measurement results show that the spurious-free dynamic range (SFDR) of the pipelined ADC is improved by 14.17dB from 64.98dB to 79.15dB, and the pipelined-SAR ADC achieves a 7.60dB improvement in SFDR from 63.00dB to 70.60dB.

This paper presents a novel calibration scheme for single-channel SAR, pipelined and pipelined-SAR ADCs using Kolmogorov–Arnold networks (KANs). In the proposed scheme, a multi-sample KAN (MS-KAN) is designed to realize nonlinear code synthesis (NLCS), achieving effective calibration for general nonlinear errors. The MS-KAN-based calibrator can be converted into an analytical expression, making the calibration process transparent, with stronger interpretability, predictability and reliability compared to previous neural network-based calibration algorithms, and assisting in the analysis of ADC nonidealities. Meanwhile, the proposed scheme achieves high calibration performance with low hardware overhead. The proposed scheme also requires much fewer training samples, thereby reducing the effort required for both chip testing and network training. The MS-KAN-based calibrator is verified with two silicon-proven ADCs, a 14-bit 1.3 GS/s pipelined ADC and a 10-bit 700MS/s SAR ADC. Measurement results show that SFDR is improved by 11.5 dB to 30.9 dB after calibration. The quantized calibrators are implemented on both FPGA and 28nm CMOS technology, where a piecewise polynomial (PWP) method is adopted to simplify the implementation of the calibrator. The post-layout simulation results show that the calibrator for the real-time calibration of the pipelined ADC consumes only 6.32 mW, while the calibrator for the SAR ADC consumes 2.42 mW.

This paper proposes a novel digital background calibration technique for interstage gain error (IGE) and gain nonlinearity in pipelined analog-to-digital converters (ADCs). Through the random switching of the multiplying digital-to-analog converter (MDAC) between two operating modes, two interstage residue curves are obtained. The IGE and the third-order gain nonlinearity are calibrated according to the distance and the geometric relationship between the two residue curves, respectively. For the proposed calibration scheme, the analog circuits require no modifications, except for the addition of several multiplexers and switches. The advantages of the proposed technique include a simple algorithm, fast convergence, and low power consumption. The simulation results show that the signal-to-noise and distortion ratio and spurious-free dynamic range of a 14-bit 1 Gsps pipelined ADC improve from 44.86 and 55.54 dB to 77.99 and 86.16 dB, respectively, after calibration. During the calibration process, the IGE and gain nonlinearity converge after 2.5 × 105and 2 × 105sampling cycles, respectively.

This article presents a new artificial neural network (ANN)-based calibration mechanism for analog-to-digital converters (ADCs). The proposed mechanism applies ANN to realize the bijective vector recovery mapping (VRM) for nonlinearity calibration and thus effectively suppresses both harmonic distortions and spurs. A new ANN-based calibrator is designed to calibrate both single-channel nonlinearity and interchannel mismatches and significantly improve the performance of ADCs. Through signal-fitting-based training process and noise adding, the proposed mechanism and calibrator can calibrate the general nonlinearity and mismatches of ADCs, including but not limited to the typical nonideality that conventional calibration techniques commonly concern (such as interstage gain error, digital-to-analog converter (DAC) error, and timing mismatch). For verification, an on-chip ANN-based calibrator is implemented in a 12-bit 600-MS/s four-channel time-interleaved (TI) ADC prototype. The measurement results show that signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.79 and 35.30 to 62.45 and 74.21 dB, respectively. Another off-chip ANN-based calibrator is applied to a commercial 12-bit 5.4-GS/s four-channel ADC, and the results show that the SNDR and SFDR are improved from 42.38 and 43.17 to 53.98 and 78.25 dB, respectively.

This paper presents a convolutional neural network (CNN) based error calibration scheme for pipelined ADC. The output of the pipelined ADC is taken as the input data of the network, and the network produces error compensation values. The network is applied in a 14-bit 1GSps pipelined ADC model with nonlinear errors including inter-stage gain error (IGE), DAC errors, thermal noise and sampling jitter for verification. The trained network scheme is verified with various types of signals including single-tone, dual-tone, amplitude modulation (AM) and frequency modulation (FM) signals. Simulation results show that, the SFDR and SNDR of the pipelined ADC are improved from 62.58dB and 58.82dB to 89.86dB and 66.66dB after calibration. Meanwhile, after calibration, the spurs of the dual-tone, AM and FM signals have been effectively suppressed.

This paper demonstrates a new neural-network-based calibration technique for inter-channel mismatches of time-interleaved ADCs. By providing with signal value and derivative value of each channel, the network could calibrate the gain mismatch, offset mismatch, and timing mismatch of TI-ADCs. By utilizing signal feature fitting, the ground truth for network training could be obtained without an accurate reference ADC nor a precise ADC error model. Simulation results show that the proposed calibration technique can increase the SFDR of a 14-bit 4Gsps TI-ADC from 32.77 dB to 91.71 dB for single-tone signals, and suppress the maximum spur from −48.51 dBFS to −101.23 dBFS for multi-tone signals. A hardware implementation resources estimation is also given in this paper.

This brief proposes a timing mismatch calibration for time-interleaved analog-to-digital converters (TI ADCs) with the novel parallel correlation derivative (PCD) technique and two-stage analog–digital hybrid compensation. The PCD technique could solve the frequency-relevant problem caused by low correlation derivative in the precise skew calculation. Besides, the compensation scheme with an analog coarse correction and then the all-digital fine correction is used to cover a larger normalized skew range and bandwidth with maintained calibration performance. Compared to previous works on timing mismatch calibration, this work has improved accuracy with a larger effective bandwidth and a larger skew calibration range. The technique is applied in a four-channel 14-bit 3 GS/s ADC model to verify its effectiveness. Simulation results show that it increases the SNDR and SFDR from 31.02 and 32.87 to 54.40 and 93.49 dB at${f}_{\text {in}}\,\,=\,\,0.99{f}_{s}$and maintains good performance in the first three Nyquist bands.

This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

This study is concerned with the application of non‐binary low‐density parity‐check (NB‐LDPC) codes to binary input inter‐symbol interference channels. Two low‐complexity joint detection/decoding algorithms are proposed. One is referred to as max‐log‐MAP/X‐EMS algorithm, which is implemented by exchanging soft messages between the max‐log‐MAP detector and the extended min‐sum (EMS) decoder. The max‐log‐MAP/ X ‐EMS algorithm is applicable to general NB‐LDPC codes. The other one, referred to as Viterbi/GMLGD algorithm, is designed in particular for majority‐logic decodable NB‐LDPC codes. The Viterbi/GMLGD algorithm works in an iterative manner by exchanging hard‐decisions between the Viterbi detector and the generalised majority‐logic decoder (GMLGD). As a by‐product, a variant of the original EMS algorithm is proposed, which is referred to as µ ‐EMS algorithm. In the µ ‐EMS algorithm, the messages are truncated according to an adaptive threshold, resulting in a more efficient algorithm. Simulations results show that the max‐log‐MAP/ X ‐EMS algorithm performs as well as the traditional iterative detection/decoding algorithm based on the BCJR algorithm and theQ‐ary sum–product algorithm, but with lower complexity. The complexity can be further reduced for majority‐logic decodable NB‐LDPC codes by executing the Viterbi/GMLGD algorithm with a performance degradation within one dB. These algorithms provide good candidates for trade‐offs between performance and complexity.