This paper proposes a physics-informed neural network model to predict the junction temperature of power devices utilized in the converter that integrates photo voltaic (PV) to the DC microgrid. The power converter operates at maximum power tracking point mode. The model considers solar irradiance, ambient temperature, output voltage of PV, and switching frequency as inputs. The model is trained using a wide range of real-world operating conditions from the National Renewable Energy Laboratory (NREL) database. The importance and utility of the proposed model are presented using two different scenarios. In one of the scenarios, the model is used to predict the duration of different overload conditions that the device can sustain. Such a prediction can help to develop prognostic methods to ensure a device operates within the allowed temperature limits. The other scenario demonstrates the modification in the switching frequency of the converter if the prediction temperature of a device exceeds the allowed limit. This scenario eliminates the need for temperature sensors and again ensures the safe operation of a device.

The Induction Motor Drives based on polygonal voltage space vector structures proposed in literature make use of switched-capacitive filtering for the suppression of lower order harmonics in the motor phase voltage. The Open-End Induction Motor (OEIM) drive systems feed the Motor with a primary and secondary inverter from either end. The primary inverter is fed with an active DC link supply, that provides all the active power for motor operation. The harmonics in motor phase voltage generated by primary inverter, are suppressed by employing a secondary inverter fed with a capacitive supply. The superposition of primary and secondary vectors generate reference vectors, that lie on the tips of a regular polygon. This work explains explains the suppression of lower order harmonics by Polygonal Voltage Space Vector Structures, by proposing a method of visualizing the harmonics in the α − β plane. The cancellation of fifth and seventh order harmonics in the reference space vector for a 42- sided Voltage Space Vector Structure will be explained using the proposed method of visualizing the harmonics. The 5thand 7thorder harmonics are canceled, as the reference vector spans a 60° duration. The suppression of said harmonics by secondary inverter, results in sixth harmonic reactive power in secondary inverter. A quantitative analysis is carried out for the design of capacitor feeding secondary inverter to maintain a small ripple in secondary inverter, while delivering sixth order power for suppression of harmonics.

The three-phase H-bridge or NPC converters are commonly adopted converter topologies for FACTS devices. Both the converters are classified as multilevel converters capable of producing a three-level AC voltage between the phase and the neutral terminals. Either topology is a good solution in the low voltage environment where it is possible to select a switch capable of blocking the required DC bus voltage. If the converter is designed for a high-voltage application, the design stage of these converters may be challenging due to making composite switches for voltage blocking requirements. Besides, there is a need for a large filter for interfacing these converters with the grid to meet the THD requirements as the operating frequency is the line frequency. Therefore, this paper adopts an MMC as an SSSC to enhance power flow in the transmission network and relieve the transmission line against abnormal situations. Besides, PR-based controllers are presented in αβ0 stationary reference frame to provide reliable operation under unbalanced grid conditions. The effectiveness of the MMC-based SSSC and its controller is modeled in FPGAs and integrated with the RTDS through fiber optic cables.

MV solid-state transformers enabled by SiC semi-conductor devices are a promising replacement to conventional transformers due to the multitude of advantages it brings along with it which includes but not limited to a smaller size, smaller weight, power flow control with reactive power capability and fault protection capability. When these MV SiC devices are used in converter applications they are exposed to high peak stress (5 kV to 10 kV) and a very high rate of change in the voltage (dv/dt) ranging from 10 kV/μs up to 100 kV/μs. Operating these devices at these high peak stresses requires intensive designing of the device package, as well as the proper design of the auxiliary systems such as the gate drivers and busbars. Recently, an extra-high voltage (XHV) power module has been developed by Wolfspeed to package the 10 kV SiC MOSFETs. This paper describes the testing of these modules in continuous operation for qualifying their operation in an MV solid-state transformer. The design and development process of the auxiliary system is also provided in brief. Successful tests demonstrating the operation of these devices at MV levels are shown. These tests serve as a qualification method for these devices for MV converter applications. It is envisaged that these devices would accelerate the deployment of MV SiC devices in on-field practical converter applications.

In recent years, the concept of solid-state transformers (SSTs) has evolved to be one of the front runners in the development and realization of a smart grid. The recent strides in the field of medium voltage wide bandgap semiconductor devices and the availability of 10 kV SiC MOSFETs and 15 kV SiC IGBTs have made it possible to build medium voltage SSTs using simple converter topologies. With the SST interfacing two grids, it forms a crucial juncture in the electrical distribution system which necessitates a high fault tolerance capacity of the SST during grid fault conditions. In addition, the grids need to be protected from any faults or abnormal operation in the SST which makes it imperative to implement different fault protection considerations on the SST. In this paper, these fault protection systems are studied in terms of their breaking time, breaking current/voltage, and fault coordination. The protection schemes are analyzed on a Gen3 10 kV SiC MOSFETs based Mobile Utility Support Equipment Solid-State Transformer (MUSE-SST) which is developed at FREEDM Systems Center aimed at interconnecting a 4.16 kV grid to a 480 V grid or load. Simulation results and are provided to evaluate the protection schemes. Initial experimental test results are also provided.

Rapid growth in the field of power semiconductor devices has enabled the development and production of medium voltage wide bandgap semiconductor devices such as 15 kV SiC IGBTs and 10 kV SiC MOSFETs. These devices have opened up opportunities for using simple converter topologies in various medium voltage applications like solid-state transformers, high-speed motor drive applications, shore-to-ship converters, etc. A medium voltage Mobile Utility Support Equipment based Solid-State Transformer (MUSE-SST) enabled by Gen3 10 kV SiC MOSFETs is developed at FREEDM Systems Center to integrate a 4.16 kV grid to a 480 V grid or a load. While these SiC devices offer a multitude of advantages in terms of lower losses and superior switching speeds as compared to their silicon counterparts, the inrush handling capacity is limited. This can prove detrimental to the power semiconductor devices and consequently the entire system if adequate measures are not taken during the startup of the solid-state transformer. This is especially critical in the case of medium voltage grid-connections due to a comparatively higher voltage level. In this paper, various startup schemes are explored for connecting the medium voltage grid to the solid-state transformer as well as different schemes for minimizing the inrush current during turn-on of the active front end converter are also shown. Simulation and initial experimental results and are provided to validate the startup schemes.

This paper presents a simple and reliable Pulse Width Modulation (PWM) and control technique for circulating current minimization of hard parallel connected Neutral Point Clamped (NPC) inverters. Interleaved operations are commonly used in parallel connected inverters for decreasing load current ripple. However, the interleaved operation increases the common mode circulating current between the hard-parallel connected inverters. To reduce the common mode circulating current, Phase Opposite Disposition (POD) PWM is used in this paper. Zero-sequence circulating currents increase, if there are any differences in DC bus voltages between parallel inverters. The zero-sequence circulating currents generate capacitor voltage unbalance in the DC bus of NPC inverters. The capacitor voltage unbalance can generate even order harmonic circulating currents. For reducing the zero-sequence circulating current, a simple DC current control method is proposed in this paper. The DC current controller decreases the circulating DC current and capacitor voltage unbalance of paralleled inverters. Finally, PLECS based simulation results of a 100kW parallel connected inverter system are presented in this paper to illustrate the effectiveness of the proposed approach.

Rapid growth in electric energy demand, increasing substantial industry restructuring, and environmental issues are imposing enormous challenges on the electrical transmission network. It is uneconomical and hard to build new generation plants for growing energy demand. Flexible AC Transmission Systems (FACTS) is a solid-state controller based technology that regulates AC systems, enhance voltage stability during steady-state and transient states if needed. Unified Power Flow Controller (UPFC) is the most versatile FACTS device to increase transmission capacity and mitigate different power system issues. This paper presents a Modular Multilevel Converter (MMC) based UPFC device for power flow and power oscillation damping control. The verification of the presented model is performed on New York Power Authority (NYPA)'s three-bus AC transmission system using Real-Time Digital Simulator (RTDS) and Xilinx Virtex-7 Field Gate Programmable Array (FPGA).

HVDC transmission is considered as an economical alternative for HVAC transmission at higher voltage levels for long distances due to bulk power carrying capability of cost-effective DC cables. The developments in the AC/DC converters, such as MMC, have made a remarkable contribution to the growth of the HVDC systems. This paper investigates soft start-up strategies for the MTDC networks, consisting of weak (SCR<; 3) or very weak AC grids (SCR<; 2). Conventional energization of an MTDC grid through pre-insertion resistors causes high surge energy and power losses. Thus, this paper adopts a two-level converter and frequency controller to provide soft energization to the DC grid, preventing high inrush current and high transients in the weak terminals. Theoretical analysis of an average large-signal model of each converter, along with its control structure, is depicted in detail. The proposed soft start-up scheme and the dynamic characteristics of the MTDC network are carried out on the RTDS.

Triple active bridge converters are an extension of dual active bridge converters and used to combine multiple energy sources. The advantages of using a triple active bridge converter are its high power density, providing isolation along with elimination of low frequency transformer and high efficiency power conversion. To address the intermittent nature of solar energy, it is always appropriate to include a energy storage device along with it. Triple active bridge converter acts a viable option in integrating these two energy sources in the most efficient manner. Further, this energy can be fed to the grid by using a voltage source converter cascaded with this triple active bridge converter. This paper discusses the cascaded converter with its control algorithms and different operating modes. A laboratory prototype of a triple active bridge converter integrated with the grid through a voltage source converter is developed and the different control and operating modes are verified, which are also included in this paper.

There is increasing interest in the development of 800V DC bus voltage architecture for long-range electric vehicles (EV). Thus three-level neutral point clamped (3L-NPC) inverter is considered an alternative topology for EV drives. Efficiency is one of the significant benefits because it enables the use of low voltage rated devices. Given this fact, this paper presents a step by step comprehensive loss analysis methodology for the determination of inverter energy loss. Using the proposed approach, the loss results for a GaN-based 3L-NPC inverter is evaluated against a SiC-based two-level (2L) inverter topology. Inverter topology selected and power semiconductor devices used are fed as input to the analytical model. The proposed model then determines the operating points of the inverter based on given motor parameters, typical vehicle-road model, and operating driving schedule. Analytical switching instances are determined, and significant semiconductor losses are computed for the complete torque-speed operating range. Energy loss and efficiency results are presented for the case of standard urban and highway drive cycles.

DC microgrids with paralleled sources require a seamless addition and removal of a converter module without shutting down the system. This replacement of a converter is known as a hot-swap event. In a democratic current sharing scheme, a critical issue is an overshoot in the grid voltage when a converter is suddenly added and an undershoot when a converter is suddenly removed. In this paper, by analyzing the start-up and shut-down operation of a converter module during the hot-swap, the reason for these excursions in the grid voltage is explained using an analytical model. It is shown that by changing the voltage controller's bandwidth, overshoot and undershoot can be reduced, but there's a trade-off between the voltage controller's bandwidth and the stability of the system. To overcome this trade-off, an algorithm that provides an additional degree of freedom is proposed in this paper. This algorithm without disturbing the system's stability prevents the overvoltage and the undervoltage by exponentially changing the current reference of the converter being added or removed. The stability analysis along with the circuit simulation results using the proposed algorithm are shown for a wide range of operating conditions and different system parameters.

DC microgrids are studied in different aspects for many years. In DC microgrids with applications such as more electric aircraft (MEA), different kinds of loads exist. Constant power load (CPL) is among the most frequent type of loads found in DC microgrids. In this paper, a DC microgrid platform with different kinds of sources and loads are considered. Droop control algorithm is utilized for the current sharing among sources. Secondary controller is employed to compensate the voltage drop due to the droop functionality. In the existence of CPLs, voltage compensation may result in increase in transmission loss. Moreover, CPLs introduce negative impedance and instability to the system. Therefore, there is a need for a comprehensive analysis to observe the stability of the system while deriving the range of CPLs to have a lower transmission loss. The proposed approach gives an idea of what percentage of CPLs to constant impedance load (CIL) yields to an improvement in voltage level as well as reduction in transmission loss. Simulation results are used to verify the effectiveness of the mathematical calculation.

Voltage-Sourced Converter (VSC) based Synchronous Static Compensator (STATCOM) is used for voltage regulation in transmission and distribution system. On the other hand, Modular Multilevel Converter (MMC) based STATCOM (M-STATCOM) is now well accepted technology in large STATCOM applications due to high modularity, scalability, and low generation of harmonics. This paper investigates negative sequence component elimination with M-STATCOM on New York Power Authority (NYPA)'s Convertible Static Converter (CSC) along with three-bus AC system on Marcy substation in the State of New York. Real Time Digital Simulator (RTDS) is used for providing the results of the study.

The use of silicon carbide (SiC) devices in medium voltage (MV) applications has become a possibility due to the development of reliable MV SiC power devices. However, when SiC devices are used in these MV applications, they are exposed to a high voltage peak stress (of up to 15 kV across the primary and secondary side of the gate driver) and a very high dv/dt (of up to 100 kV/μs across the isolation transformer). The gate driver design is very critical for proper functioning of the MV devices under the presence of such high dv/dt. This paper presents a design of an improved gate driver power isolation method, with a low coupling capacitance between the primary and the secondary side. The footprint of the isolation transformer is minimized to meet the clearance and insulation requirements. Comparisons have been drawn with an existing gate driver topology, on the basis of size of the gate driver, and common mode performances for different dv/dt. Experimental results are provided to validate both the gate driver designs. The testing and analysis is carried out on a 10 kV SiC MOSFET developed and packaged by Wolfspeed. In addition, a brief discussion on the insulation standards for these kinds of applications is provided. The gate driver concept is aimed at providing a benchmark for building an efficient and reliable method to drive MV SiC devices.

Droop control as a well known approach is used as the basis of the power sharing among different paralleled voltage sources and battery energy storage systems (BESS). In order to extend the lifetime of BESS and avoid the overuse of a certain battery, the State of the Charge (SoC) of BESS should be balanced. This paper reviews and compares three different droop control methods in an islanded DC microgrid that are based on balancing the SoC of different BESS. All of the presented methods are compared together and the best one is selected. The feasibility of the selected method is verified through computer simulations in MATLAB/Simulink for a DC microgrid consisting of three BESS, PV (Photovoltaic) arrays and DC load.

Nowadays, DC microgrids by linking DC sources such as renewable resources directly to the DC loads and offering higher efficiency due to the elimination of conversion stages are gaining more and more popularity. In DC microgrids with renewable resources, there are stochastic behavior and uncertainties. Thus, energy storage use is unavoidable. Droop control as a well known method is used as the basis of the power sharing among different parallel voltage sources and battery energy storage systems (BESSs). In order to extend the lifetime of BESSs and avoid the overuse of a certain battery, the State of the Charge (SoC) of BESSs should be balanced. This paper presents a review on three different droop control based methods for balancing SoCs of different BESSs in DC microgrids. Moreover, the paper proposes a new droop control method for SoC balancing to overcome the drawbacks of the mentioned methods. The mathematical model of these different methods are derived using small signal state space modeling for a Photovoltaic (PV) grid-interactive DC microgrid consisting of two BESSs. Then, a comparison study has been performed for the mentioned four methods using MATLAB/Simulink.

This paper presents a novel architecture to integrate the photovoltaic and energy storage to the grid. The modular approach is provided by using the triple port active bridge DC-DC converter modules and the cascaded H-Bridge multilevel inverter structures. The modular approach helps in easy scaling up, easy maintenance and better controllability of the available power. The triple port bridge is capable of supplying and receiving power in any of its ports, allowing various control modes. Also the voltage control mode at its output allows for additional grid services. The cascaded H-bridge is a multilevel inverter with higher number of voltage levels, reduced filter size, lower switching frequency, lower dv/dt and EMC issues. The experimental and simulation results presented in this paper ensures that the proposed architecture is suitable for large scale photovoltaic and energy storage grid integration.

The development of fully controlled power semiconductor devices has paved way the path for Voltage Source Converters (VSC) based High Voltage Direct Voltage (HVDC) transmission systems. For these high voltage applications, Modular Multilevel Converter (MMC) is a good candidate which utilizes interconnection of several Sub-Modules (SM). Furthermore, it provides several advantages including flexibility, scalability, better voltage quality etc. However, the MMC can be vulnerable to the DC short circuit faults. Different Sub-Module (SM) topology based MMCs exists which can suppress the DC short circuit current. The MMCs can be modelled with different modelling technics. This paper presents a comparative study of a point to point (PTP) MMC based HVDC system with feed-forward current control based on detailed and averaging modelling technics. Furthermore, the DC short circuit handling capabilities of Half Bridge SM (HBSM) and Full Bridge SM (FBSM) topologies are examined. Real time simulation results are provided to demonstrate the results of the study on FPGA based MMC support unit from Real Time Digital Simulator (RTDS).

Solid state transformers (SSTs) are evolved as an emerging technology which offer several key features in integrating different grids, storage devices, and renewable energy sources, etc. In this paper, a 10 kV SiC MOSFET enabled Mobile Utility Support Equipment based SST (MUSE-SST) is presented for integrating a medium voltage (MV) AC grid (4.16 kV L-L, 60 Hz) and a low voltage (LV) AC grid (480 V L-L, 60 Hz). The MUSE-SST consist of three power conversion stages: MV side active front end converter (AFEC: MV), dual active bridge (DAB), and LV side active front end converter (AFEC: LV). In order to protect MUSE-SST from various abnormal operating conditions, different protection schemes are discussed. Dedicated gate drivers incorporating device short-circuit protection are implemented for both the MV and the LV SiC MOSFETs. It is observed that the MV short circuit faults are found to be severe and resulting in very high inrush currents from the MV grid which can lead to the impairment of entire SST system. A bi-directional switch in parallel with a high impedance resistor (BSPHR) circuit based protection scheme is presented to limit the grid currents during MV dc-link short circuit conditions. The BSPHR scheme and efficacy of gate drivers are validated through simulations and experimental results, respectively. The avalanche ruggedness of 10kV, SiC MOSFETs is established experimentally using a single shot unclamped inductive switching (UIS) test and the critical avalanche energy for the MOSFET failure is obtained.

This paper presents a design strategy of a dv/dt filter for high speed machine drives based on analytical analysis. Both a LCR filter and a LC with a diode bridge are studied and, a choice between two options can be made depending on a length of cable. The way of choosing the value of L, C, and R of the filter is proposed by analyzing the transfer function of the filter output voltage and the filter resonant current. In the same manner, filter characteristics such as dv/dt, rise time, peak voltage, and peak resonant current can be adjusted accurately. The power loss in damping resistors are discussed. The proposed design scheme is evaluated through simulations and experiments with a SiC inverter and high speed IPMSM.

Modeling of dual active bridge (DAB) type converters, and that of its single-phase form, is an active area of research. In this paper, a new modeling approach is proposed. It is theorised that single-phase DAB converter operating in any of its multiple modes and modulation may be modeled as four dual active half-bridge (DAHB) circuits operating in simple phase-shift modulation. It allows extension of the model developed for simple phase-shift modulated DAHB converter to any operating mode of the DAB converter. In this respect, the physical basis of the theory is first explained. Subsequently, the improved first harmonic approximation (I-FHA) model of the DAHB converter, developed a priori, is extended to the general operating case of the DAB converter. Finally, the model is validated through extensive simulation and hardware experiments proving the theoretical basis of the proposed approach.

This paper proposes a hybrid 7-level inverter scheme formed by cascading basic inverter cells. The proposed inverter is realized by cascading basic 3-level T-type converter with 5-level active neutral point clamped inverter. The proposed topology uses low voltage semiconductor devices and floating capacitors which are balanced in every PWM switching cycle using pole voltage redundancies for every pole voltage levels. The balancing of capacitors are independent of modulation index and load power factor. The topology forms two stacks at the front-end which uses individual symmetrical reduced DC sources and each stack works only for half the fundamental period. The open loop V/f control is simulated as well as experimentally verified on induction machine using proposed inverter topology. The experimental and simulation results for transient and steady state operations are included in the paper. Further, a brief comparison of proposed topology with conventional 7-level topologies have also been included.

The work presented in this paper focuses on the transformer modelling, design and parasitic capacitances' effect on transformer operation for three-limb high frequency transformers designed for three port Dual Active Bridge(DAB) converter, using 1200V and 1700V SiC devices. The effects of parasitic capacitance due to high speed and high frequency switching enabled by SiC Mosfet devices are investigated in this paper for three limb transformer of DAB converter. The focus of the paper is based on design, estimation and measurement of parasitic capacitance and leakage inductance for three limb high frequency transformer. Detailed transformer model analysis has been realized for three port DAB operation with parasitics included. Two different transformer design approaches for 10kW, 50kHz rating have been carried out and comparative results have been analyzed in this paper.

This paper presents a synchronous reference frame full-order observer for a three-phase buck-type PWM rectifier that estimates both the currents of the input filter inductors and the voltages of the input filter capacitors. Either the currents or the voltages are needed in most cases to control the input grid power factor and the output dc voltage or current. For example, multiloop control strategies, which have been widely used for power rectifiers that are equipped with higher order LC or LCL input filters, require input filter currents or voltages. Using the proposed observer, the number of actual sensors needed for a buck-type rectifier control system can be reduced while maintaining fast dynamic performance and steady-state accuracy. The feasibility of the proposed technique is verified through MATLAB/PLECS simulations and experiments.

In order to synchronize the distributed control systems (DCS) in modular converters such as Advanced Modular Multi-level Converters (AMMC) and Modular Transformer Converter (MTC) to the supervisory controller, a network layer must be established, and appropriate control architecture must be designed. In this paper, different control architectures for DCS with application in AMMC and MTC including series (daisy chain), parallel, and parallel-daisy (using both serial and parallel setup) are explored. There are practical issues in synchronization of modules in modular converters that have been addressed by and given solution to in the paper. The laboratory experimental test beds for MTC and AMMC configurations with distributed control systems (series (daisy chain), and parallel) architectures are implemented and experimental results are presented to validate the distributed control configurations.

The basic principles of UPFC operation are discussed and the series inverter dynamics are explained. Two control strategies - the Cross-Coupling method and the Advanced Control method are discussed in detail and their bode plots are analyzed. The two control methods are implemented in PSCAD for the NYPA UPFC at Marcy substation. The performance of the two methods is observed for step changes in active power reference and the results are compared.

This paper introduces a variable interleaving technique for photovoltaic cascaded DC-DC converters. A series rather than parallel connection of converters allows higher switch utilization and lower rating of components; however, they suffer from nonhomogeneous irradiations condition. Under partial shading conditions, the input power of all PV panel will not be the same and as a result the output voltage of each converter will not be identical. This causes system to operate in an asymmetric condition, in which, the conventional interleaving techniques are not capable of eliminating the DC link output voltage variations. In this work, an interleaving algorithm is reported on cascaded DC/DC converters under asymmetric condition to minimize the DC link output voltage variations. The effectiveness of this algorithm for cascaded DC-DC converters has been validated by simulation and Hardware-In-the-Loop tests.

One of the main limitations in using high voltage and medium voltage DC grids is the issues related to the current-limiting devices and circuit breakers. These devices should be able to handle large currents in the normal operation condition and block high DC currents in a few microseconds in the case of DC faults. Moreover, they are required to dissipate huge amounts of energy stored in the transmission line inductances. In this paper, four configurations of DC circuit breakers from three general groups are evaluated and the results are compared in terms of the time required by the breakers to interrupt the current, maximum DC breaking current, rated voltage, efficiency and current state of development. The performance of DC circuit breakers is evaluated when a line to ground DC fault happens in a 9 module/2 terminal DC system. Simulation results were obtained using Real Time Digital Simulator (RTDS) and PSCAD.

A high power Y : Y/Δ three-phase Dual Active Bridge (DAB) topology offers higher power density, smaller switching stress, smaller volume of magnetics and smaller DC capacitor over single phase DAB. Therefore this topology is suitable for medium voltage (MV) applications. The high-frequency DAB currents are nearly sinusoidal suited for D-Q transformation which enables fast average mode current control for device protection. But it requires fast ADC conversions and processing speed to implement this control. Also the PWM channel requirement for this topology is high. A DSP repeats an infinite loop of calculations serially. Thus it has limited loop speed in case of longer algorithm size which limits the control bandwidth. An FPGA based control is suitable as it can process the algorithm in programmable combinational logic circuits which offer few nano-seconds of propagation delay. And thus the only speed limitation is the ADC conversion speed. But an FPGA board does not readily offer all the features required for this application. Therefore an ultra-fast 2 MSPS parallel ADC interface board has been developed to achieve the control objectives for the topology in this paper.

This paper presents a novel approach to control power flow inside a high frequency transformer based multiport DC-DC converter. A multiport converter can interface a number of power sources and sinks with control of power flow among them. In a renewable energy sources (RES) integration scheme, the multiport converter operates like an accumulator where it collects power from each RES and dispatches it to the load port. Typically, power flow between any two ports happens through the leakage inductance of the transformer by imposing a required phase shift between fundamental component of two square wave voltages, impressed at the ports. However, each port is connected with the other ports by some inductance and hence the power flow from a particular source port to load port is not decoupled and can not be controlled independently. This paper proposes decoupling of source ports by eliminating the load port leakage inductance with a negative inductance, emulated by voltage injection in series with leakage inductance. A three port transformer based system is simulated to validate the principle. A scaled prototype of the three port transformer is designed and the effect of load port leakage inductance is analyzed through experiment.

For industrial applications requiring medium and high-power supplies modular multilevel converter (MMC) based voltage source converters (VSC) offer advantages over traditional VSCs. These include achievement of higher voltage levels with utilization of lower voltage power semiconductor devices. The control structure of MMC for fault operating condition is proposed in this paper, and dynamic performance of the MMC based on the proposed control structures is further investigated in PSCAD/EMTDC environment. Real Time Digital Simulator (RTDS) results are also presented to verify the controller performance under normal and fault operating conditions.

The Convertible static transmission controller is a versatile device which can be installed across a transmission transformer to extend the life time of existing transformers by partially bypassing and conditioning the substation throughput power. The proposed technology can provide several integration options with multiple operational modes. From the supervisory control point of view, a control algorithm is required to set the reference values of active and reactive power flow of CSTC converters based on the desired operating points for transformer active and reactive power. In this paper, the algebraic model of CSTC in shunt-shunt mode of operation is derived. Algebraic model of CSTC is used for steady state and transient stability analysis. Algebraic model will present the behavior of transformer power flow with respect to various operating points of CSTC converters. The P-Q transformer operating range can be obtained based on the proposed algebraic model. Dynamic performance of the CSTC system is also investigated in PSCAD/EMTDC environment. Simulation results will be presented to verify the proposed algebraic model of CSTC in shunt-shunt mode of operation based on steady state results.

Convertible Static Compensator (CSC) which is a versatile Flexible AC Transmission System (FACTS) technology has been installed on Marcy 345 kV substation and increases power transfer capability, operational functionality, and power flow controllability of the New York Power Authority (NYPA) transmission system. This paper presents a comprehensive description of CSC inverter 48-pulse wave construction along with introduction of control strategy deployed in CSC when it is operating as a STATCOM and UPFC. STATCOM and UPFC steady state and dynamic operation PSCAD simulation results under different testing conditions including unbalanced condition and faults are presented. This paper also provides comprehensive analysis of the STATCOM response to negative sequence and harmonic voltage components on the transmission line during fault conditions. The amounts of DC-link capacitance that lead to maximum and minimum of fundamental negative sequence current on the tie line and 120 Hz oscillation on the DC-link voltage are calculated. Simulation results of STATCOM performance with different DC-link capacitance during fault condition will be shown. At the end of the paper, one exiting problem regarding to UPFC operation of NYPA CSC has been addressed and illustrated with precise simulation results.

This paper presents smoothing of oscillatory power generated by a wave energy converter (WEC) from sea wave. WEC oscillates in sea wave and an electrical generator connected to it generates oscillatory power of typical period of oscillation of 6 to 10 seconds. This power can not be directly fed to a load or grid and hence an energy storage device is required to filter out the oscillation. Super-capacitor (SC) is a better choice over battery as an energy storage device due to its low maintenance requirement and better power capacity. A WEC is emulated in hardware using induction motor (IM) and a permanent magnet synchronous machine (PMSM) is used as the generator. Power generation from WEC is controlled by controlling PMSM current. Power flow to and from SC is controlled to smooth the power output. The overall control system is implemented in hardware and smoothing of the oscillatory power using SC is demonstrated.

Electric Arc Furnaces (EAFs) are among the larger loads imposed upon the electrical grid. The size of these loads, when combined with the stochastic nature of the electric arc, and the poor reaction of the grid to such loads, makes the EAF worthy of study in general and modeling in particular. The present work develops a model of an EAF that is designed as a custom component for use with the PSCad modeling software but can be used equally well in real-time simulation systems. The model is single-phase, allowing multiple instances to be connected in any configuration so that unbalanced situations can be easily simulated. The model is completely documented so that it can be duplicated with no additional information.