Haoyang Shen

dblp:119/7433 · DBLP profile ↗
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5ranked-venue papers
4as first author
5since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author · 4 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2025 The Curious Case of Seed-Related Fractional Spurs
abstract
Fractional-N frequency synthesizers are notorious for producing spurious tones (spurs) whose frequencies depend explicitly on the fractional part of the frequency control word. This paper addresses spurs that appear in the spectrum when that fraction is zero. In principle, this setting should not produce any spurs other than the reference spur and its harmonics. In practice, if the divider controller is clocked, it introduces a set of spurs whose locations are determined explicitly by its initial state (usually called the "seed"). Experimental observations are consistent with theoretical analysis and simulations.
Michael Peter Kennedy, Haoyang Shen, Sonia Srinivas
ISCAS3
2025 Enhanced CppSim-Based Behavioral Simulator for Predicting Noise Floor and Spurs in Fractional-N Frequency Synthesizers
abstract
A fractional-N frequency synthesizer inherently generates spurious tones because its output frequency is not an integer multiple of the reference frequency. Its spectral performance is degraded by these spurious tones that are caused by memoryless nonlinearities. This paper describes a CppSim-based behavioral model which can predict the effects of a user-defined arbitrary nonlinearity in terms of noise and spurs. The simulator is demonstrated for various divider controller architectures, such as multi-stage noise shaping (MASH), successive requantizer (SR), and enhanced nonlinearity-induced noise performance (ENOP). The enhancements successfully address the limitations of the basic CppSim model and provide various interfaces for accessing data related to VCO phase noise and spectrum analysis.
Haoyang Shen, Michael Peter Kennedy
ISCAS1
2024 FEC-Aided Decision Feedback Blind Mismatch Calibration of TIADCs in Wireless Time-Varying Channel Environments
abstract
Time-interleaved analog-to-digital converters (TIADCs) are widely used in communication systems due to their exceptionally high sampling rates; however, in real-world applications, the offset, gain, and time-skew mismatches in TIADCs are a significant challenge for the circuit system. This article proposes a forward error correction (FEC)-aided decision feedback blind mismatch calibration for TIADCs in the time-varying channels environment specific to the orthogonal frequency-division multiplexing (OFDM) system. In our proposed approach, we use an FEC decision feedback technique to generate a ground truth reference signal for the purpose of calibration. There are two stages. In the first stage, the offset and gain mismatches are estimated and corrected using standard techniques. In the second stage, an adaptive filter bank corrects the time-skew mismatch directly without the need for any additional calibration hardware. The coefficients of this adaptive filter are continuously adjusted in the background based on an error signal derived from the decision feedback ground truth signal. This calibration algorithm significantly reduces the bit error rate (BER) and improves the system performance. The efficacy of these approaches is validated through comprehensive simulations to attain a performance assessment, quantified by the BER, using a realistic wireless time-varying channel system configuration.
Haoyang Shen, Chacko John Deepu, Barry Cardiff
IEEE Trans. Very Large Scale Integr. Syst.1
2023 A Multi-level Synthesis Strategy for Online Handwritten Chemical Equation Recognition
Haoyang Shen, Jianmin Lin, Wei Wu 0019
ICDAR (1)1
2023 A Foreground Mismatch and Memory Harmonic Distortion Calibration Algorithm for TIADC
abstract
This paper proposes a foreground digital calibration algorithm that estimates and corrects the offset, gain, and time-skew mismatches for time-interleaved analog-to-digital converters (TIADCs) furthermore our algorithm is designed to correct for harmonic distortion introduced by the presence of a nonlinear front-end. We propose a novel simplified non-linear model in place of the more complex conventional Volterra series based structure. The mismatch estimation technique based on the Fast Fourier Transform (FFT) is proposed to estimate the various time-interleaving mismatches simultaneously. A Taylor-based technique is applied to compensate for these mismatches. We also consider the choice of an appropriate time reference for the time-skew correction algorithm by theoretical analysis. The nonlinear distortion correction technique is based on estimating and inverting an assumed$3^{\text {rd}}$order nonlinearity with a fractional delay. To do this, we design a customized filter in an offline process. Our algorithms are designed to operate in any Nyquist zone. The proposed techniques are verified by a Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit containing a 12-bit, 4.096 GHz TI-ADC with 8 sub-ADCs operating in the$2^{\text {nd}}$Nyquist zone. Accordingly, we observed an improvement in SFDR of 14 dB for mismatch calibration alone and up to another 12 dB with nonlinear correction enabled.
Haoyang Shen, Adam Blaq, Chacko John Deepu, Barry Cardiff
IEEE Trans. Circuits Syst. I Regul. Pap.1