This paper presents an efficient 8-MS/s 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed symmetric complementary switching (SCS) and split passive reference segmentation (SPRS). Conventionally, improving the SAR ADC speed compromises the signal-to-noise-and-distortion ratio (SNDR) and energy efficiency due to the high precision requirement and the sequential bit-cycling. In this design, the proposed SCS scheme reduces the parasitic capacitance in the sampling path and the settling error of the capacitive digital-to-analog converter (CDAC) with low SNDR and hardware penalties. In addition, to reduce reference ripples, active reference buffers generally consume high power while the passive methods may degrade the SNDR or occupy large areas. To efficiently reduce reference settling errors, an area-efficient SPRS is developed, which suppresses the reference settling error through the split reference segmentation. The prototype chip is fabricated in a 180-nm CMOS process and occupies an area of 0.57 mm2. Measurements show the ADC achieves a peak SNDR of 89.2 dB at 8 MS/s with a 9.5-mW power consumption. The Schreier-figure-of-merit (FoM) is 175.4 dB.

This paper proposes an information-aware (IA) adaptive data acquisition (ADA) system for the Internet of Things (IoT) applications. The system can obtain valid information adaptively thanks to 1) signal-dependent full-scale feature tracks the amplitude-domain activity of the event; 2) level-crossing (LC) ADC with slope detector delivers the time-domain activity; 3) the IA algorithm determines the quantization resolution according to the detected signal activities. The proposed clock-free event-driven ADA system can reject the redundant data, and compress the valid data from the source, thus saving its power and the power of subsequent data-processing systems. The long-term average power consumption of the system is 128 nW, the resolution varies from 3 to 7 bits according to the input signal state. Compared with conventional ADCs, LC-ADC can compress the data by 2.5x [1]. Further, the proposed system has 15x higher compression ratio (CR) than that of LC-ADC.

This work presents an application specific integrated circuit (ASIC) working as an electrical vagus nerve stimulation (VNS) system targeting emerging VNS-based point-of-care treatments where such a system needs to be implanted within the human body. Implemented in a 180 nm Bipolar-CMOS-DMOS (BCD) process, the ASIC is capable of delivering accurate stimulation current, and can support stimulation voltages up to 15 V. Such a high voltage compatibility provides extra room for variances in tissue impedance under the same requested stimulation current. The design is tested with a commercial-grade platinum helical electrode, and shows a maximum output current of 7 mA when the electrode is submerged in phosphate-buffered saline (PBS), and a low standby power of$9.63\ \mu\mathrm{W}$. The low power, small area, high output current resolution, and process's compatibility with direct processor integration all make this design a promising candidate for a single-chip implanted VNS system.

This paper presents a dual-phase RC-based relaxation oscillator (RxO) with low temperature coefficient (TC) and high power efficiency achieved simultaneously for energy-constrained Internet-of-Things (IoT) applications with burst-mode requirements. Its circuit-level event-driven architecture reduces the duty cycle of power-hungry blocks, saving power while posing little performance penalty. In addition, the charge reuse technique further reduces the power consumption for the always-on detecting circuit. Implemented in a 0.18-μm CMOS process, the 180-kHz relaxation oscillator exhibits a frequency deviation of ± 0.26% against temperature (-40 to 125 ° C) from Monte-Carlo simulation (N=30), leading to a low temperature coefficient of 32 ppm/° C. The simulated power consumption is 163 nW, resulting in power efficiency of 0.9 nW/kHz.

High power consumption is usually required in a spin-torque-transfer magnetoresistive random access memory (STT-MRAM) array’s peripheral circuits for reliable operations. In read, power needs to be spent for the low absolute resistance in the magnetic tunnel junctions (MTJ), and a limited high-state-to-low-state resistance ratio calls for high currents for the same detectable readout voltage under accuracy requirements. In write, the random programming time poses challenges for energy efficient write operations within an acceptable write error rate. To address the issues mentioned above, in this work, we propose a reliability-improved read circuit that consumes only 92.09 fJ/bit read energy while ensuring correct readout values under 4.5 sigma resistance variance, and a self-terminating write peripheral circuit achieving an energy reduction of 82.3% at 1 part-per-million write error rate (WER) under 20 ns write period.

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.