The efficient execution of Java programs presents a challenge to hardware and software designers alike. The difficulty, however, lies with the Java bytecodes. Their model of a simplistic, platform-independent stack machine is well-suited for portability, though at the expense of execution speed. Various approaches are being proposed to increase the speed of Java bytecode programs, including: (i) on-the-fly compilation to native code (also known as JIT or ‘just-in-time’ compilation); (ii) traditional (‘ahead-of-time’) compilation of bytecodes to some higher-level intermediate form and then to native code; and (iii) translation of bytecodes to a higher-level language and then use of an existing compiler to produce native code. Speedups of the order of 50 over standard bytecode interpretation have been claimed. All of these approaches rely upon bytecode analysis (of varying sophistication) to extract information about the program, which is then used to optimize the native code during the translation process. However, extracting information from a lower-level representation such as the Java bytecodes can be very expensive. Also, given the fact that most approaches for executing Java bytecodes cannot spend a great deal of time recovering high-level information, the solutions adopted during the translation process must use faster and less accurate analysis techniques, thus penalizing the quality of the native code. In this paper we propose an optimization approach based on bytecode annotations. The bytecodes are annotated during the original source code to bytecode translation, allowing both traditional interpretation by a JVM and aggressive optimization by an annotation-aware bytecode compiler. Annotations hinder neither portability nor compatibility, while preserving optimization information that is expensive to recompute. Preliminary results yield bytecode with C-like performance using JIT technology. © 1997 John Wiley & Sons, Ltd.

This paper presents a new transformation for the scheduling of memory-access operations in high-level synthesis. This transformation is suited to memory-intensive applications with synthesized designs containing a secondary store accessed by explicit instructions. Such memory-intensive behaviors are commonly observed in video compression, image convolution, hydrodynamics and mechatronics. Our transformation removes load and store instructions which become redundant or unnecessary during the transformation of loops. The advantage of this reduction is the decrease of secondary memory bandwidth demands. This technique is implemented in our Percolation-Based Scheduler which we used to conduct experiments on a suite of memory-intensive benchmarks. Our results demonstrate a significant reduction in the number of memory operations and an increase in performance on these benchmarks.

One of the challenging tasks in code generation for embedded systems is register assignment. When more live variables than registers exist, some variables will necessarily be accessed from data memory. Because loops are typically executed many times and are often time-critical, good register assignment in loops is exceedingly important as accessing data memory can degrade performance. The issue of finding an optimal register assignment to loops has been open for some time. In this article, we present a technique for optimal (i.e., spill minimizing) register assignment to loops. First we present a technique for register assignment to architecture styles that are characterized by a consolidated register file. Then we extend the technique to include architecture styles that are characterized by distributed memories and/or a combination of general- and special-purpose registers. Experimental results demonstrate that although the optimal algorithm may be computationally prohibitive, heuristic versions obtain results with performance better than that of an existing graph coloring approach.

In this paper we present a new transformation for the scheduling of memory accessing operations in High-Level Synthesis. This transformation is suited to memory-intensive applications with synthesized designs containing a secondary store accessed by explicit instructions. Such memory-intensive behaviors are commonly observed in video compression, image convolution, hydro-dynamics and mechatronics. Our transformation removes load instructions which become redundant during the transformation of loops. The advantage of this reduction is the decrease of secondary memory bandwidth demands. Our experiments on benchmarks from several application areas show that a significant reduction in the number of memory loads is obtainable.

The major ATM switch architectures and their improvement techniques are categorized and discussed, focusing on performance issues. The performance measures of interest are the maximum throughput, the delay time, and the cell loss probability. The major assumptions and notations used are summarized. A survey is presented of nonblocking switches and their improvement techniques. The performances of a variety of nonblocking switches are compared.>