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D. Prodanos

dblp:12/1556 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 39% Integrated circuit design · 30% Processor architecture and microarchitecture · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.112006
A Metric for Automatic Word-Length Determination of Hardware Datapaths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Processor architecture and microarchitecture › computer arithmetic
fixed-point arithmetic		 0.112006
A Metric for Automatic Word-Length Determination of Hardware Datapaths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation
high-level synthesis		 0.112006
A Metric for Automatic Word-Length Determination of Hardware Datapaths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation
design space exploration		 0.012006
A Metric for Automatic Word-Length Determination of Hardware Datapaths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006

Methods — techniques the papers use, named apart from their topics

fixed-point simulation · 0.1error modeling · 0.1
YearPublicationVenuePosition
2006 A Metric for Automatic Word-Length Determination of Hardware Datapaths
abstract
A metric for the automatic determination of word lengths required for implementing DSP algorithms is proposed. The metric is capable of handling several error models computed between the fixed-point and the floating-point simulation results to model the impact of finite word lengths on the overall accuracy. It grades all the word-length combinations and guides a procedure towards the optimal solution. This metric was implemented in an automatic word-length determination tool to guide its search for better hardware implementations. It enables the creation of a framework for architecture and platform exploration.
Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3