As the demand for high-speed memory interfaces continues to grow, the need for effective testing methodologies becomes increasingly critical. Traditional automatic test equipment (ATE) systems are limited in their capability to test advanced signaling methods such as pulse amplitude modulation-4 (PAM-4) due to their reliance on non-return-to-zero (NRZ) signaling. This article presents a PAM-4 transceiver designed to bridge the gap between the tester and the memory, boosting the PAM-4 testing data rate up to 48 Gb/s using existing NRZ-based ATE. The proposed work provides enhanced transition slope and ratio level mismatch (RLM) control through precise gate voltage adjustment, resulting in improved test accuracy. The prototype was fabricated in 40-nm CMOS technology and occupies an active area of 2.34 mm2. The proposed work operates at 48 Gb/s/pin, demonstrating an energy efficiency of 1.85 pJ/bit in write mode and 2.97 pJ/bit in read mode for the PAM-4 test, respectively.

This brief proposes a digital phase-locked loop (DPLL) with a power supply noise (PSN) regulated ring-type digitally controlled oscillator (DCO) using an nMOS shunt regulator array. The proposed nMOS array dynamically detects the PSN and creates a pathway, channeling the PSN forwarded through the digitally controlled resistor (DCR) directly to the ground. To support the proposed power supply noise compensation (PNC) technique in wide-range operation, the output bits from the digital loop filter (DLF) control not only the DCR but also the total transconductance of the nMOS array. The supply-sensing amplifier (SSA) between the supply and the gates of the nMOS array amplifies supply noise to lower the voltage headroom, allowing the DCO to run faster. Fabricated in 40-nm CMOS technology, the prototype DPLL demonstrates an rms jitter of 1.27 ps under 1 MHz, 20-mVPPsinusoidal noise, while the rms jitter without the regulator is measured as 3.26 ps. The total power consumption and area occupation of the DPLL are 13.5 mW and 0.066 mm2, respectively. The proposed scheme for PNC contributes only 1.90 mW and 0.0017 mm2, representing 14.1% and 2.8% of the total, respectively.

A change from a non-return-to-zero (NRZ) signaling to a four-level pulse amplitude modulation (PAM-4) signaling causes various challenges in clock and data recovery (CDR) designs as well as analog-front-end (AFE) designs. A PAM-4 CDR with a 2x-oversampling phase detector (PD) has an issue of increased pattern-dependent jitter due to asymmetric transitions. This work investigates a similar problem in a baud-rate CDR by analyzing the PD characteristics. In the PAM-4 baud-rate sampling, the transitions are classified into two types: full-swing transitions and non-full-swing transitions. Since utilizing the non-full-swing transitions can affect the jitter tracking ability, careful consideration of decisions using these transitions is necessary to optimize the jitter performance. To address this issue, we propose an asymmetric-weighted PD that minimizes pattern-dependent jitter and maximizes a transition density by utilizing both the full-swing transitions and the non-full-swing transitions. Using a pseudo-linear analysis, the proposed PD achieves improved jitter performance compared to the conventional PD. Fabricated in 28-nm CMOS process, a prototype PAM-4 receiver with the proposed CDR is demonstrated at 40 Gb/s. The CDR achieves a bit error rate (BER) less than 10$^{-9}$and an energy efficiency of 1.65 pJ/b.

This paper presents a 50-Gb/s receiver (RX) with an adaptive phase-shifting (APS) phase detector (PD) for four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR). The APS PD adopts a$\beta $detector to achieve a unique locking point that resolves the dead-zone problem caused by the combination of the conventional baud-rate PD and adaptive decision feedback equalizer (DFE). The APS CDR is configured with a sign-sign minimum mean squared error (SS-MMSE) PD and an addition of a digital coefficient which is adaptively controlled through the$\beta $detector by detecting pre-cursor inter-symbol interference (ISI) dependency of 1-level transitions. Therefore, the proposed CDR does not rely on external coefficients. Furthermore, adaptive programmable gain amplifiers (PGAs) and DFE are implemented with the APS CDR to compensate the pre and post-cursor ISIs, and main-cursor level. Since the adaptive equalizers and the APS CDR share the error samplers, no additional analog hardware is required. Fabricated in 28-nm CMOS technology, a prototype PAM-4 RX operates at 50 Gb/s and occupies an active area of 0.16 mm$^{2}$. The RX tested over a 25.3-dB loss channel achieves a bit error rate (BER) of less than 10$^{-12}$and energy efficiency of 2.52 pJ/b.

This paper presents a 14–28 G/bs reference-less Baud-rate clock and data recovery (CDR) with a stochastic phase and frequency detector (PFD). To achieve phase and frequency detection, optimum weight is determined through the histogram-based correlation of various data patterns. Many data patterns within a wide frequency range are utilized to demonstrate robust operation. The reference-less Baud-rate CDR is implemented utilizing data samples and phase error samples obtained from the integrator. The proposed CDR is designed to achieve a data rate of up to 28 Gb/s employing a continuous-time linear equalizer (CTLE) under a 4.7-dB data loss channel at Nyquist frequency. Fabricated in 28-nm CMOS technology, the proposed CDR achieves a bit error rate (BER)−12and energy efficiency of 1.06 pJ/b.

This paper presents a 48-Gb/s single-ended PAM-4 receiver (RX) with an adaptive nonlinearity compensating equalizer. The receiver incorporates 3 parallel Cherry-Hooper continuous-time linear equalizers (CTLEs) and a 1-tap 9-coefficient adaptive decision feedback equalizer (DFE). CTLEs provide a variable gain with offset-canceling calibration. The DFE detects the level separation mismatch ratio (RLM) of the transmitted data and nonlinear distortion within the receiver analog front-end (AFE). The nonlinearity is compensated by simultaneously adapting 9 coefficients of the nonlinearity compensator. The proposed RX is fabricated in the 40nm CMOS technology, occupying 0.236 mm2. Measured in a 7-dB loss channel, the RX achieves a BER of less than 10−12and energy efficiency of 2.97 pJ/b.

This article presents the design of an area/ power-efficient discrete-time (DT) delta-sigma ($\Delta \Sigma $) modulator suitable for multichannel sensor applications. First, the area efficiency of the modulator is achieved by optimizing the size of the sampling capacitor with the compact integrators based on the dynamic-boost inverter (DBI). The DBI is designed to have a small active area of only 0.00044 mm2, due to its self-bias scheme that eliminates the need for additional hardware for biasing circuitry. Second, the power efficiency is improved through the quantitative design approach to reduce the power consumption of the integrators by optimizing the gain–bandwidth product (GBW) of the DBI-based OTA in each integrator. In addition, the static current consumption of the integrators is further reduced due to the power-saving feature of the DBI utilizing the principle of a composite transistor. Finally, the self-bias scheme ensures that the DBI maintains a dc gain of 44.3 dB despite circuit mismatch by balancing the currents of the nMOS and pMOS transistors in the DBI. The prototype modulator, fabricated using 0.18-$\mu \text{m}$CMOS technology, occupies an active area of 0.0939 mm2. For a 25-kHz bandwidth (BW), the modulator achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 84.0 dB, a peak SNR of 85.1 dB, and a DR of 87.1 dB with a power supply rejection ratio (PSRR) of 56.8 dB and a common-mode rejection ratio (CMRR) of 66.1 dB at a 1.8-V supply. The modulator also maintains an SNDR higher than 82.5 dB and a DR higher than 85.5 dB for a 5–25-kHz BW with an${\mathrm {FoM}}_{W}$of 78.4–103.4 fJ/conversion at a 1.5–1.8-V supply.

This article presents a fully passive noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) that can be compatible with dynamic voltage and frequency scaling (DVFS) schemes while offering a 12-bit resolution for Internet-of-Things (IoT) sensor applications. To realize a voltage-scalable suppression of the in-band quantization noise, the proposed ADC utilizes a second-order cascade of integrators with feedforward (CIFF) NS loop with a 3-input dynamic comparator, which can obtain an additional resolution of more than 3 bits. A cyclic dynamic element matching (CDEM) for MSB is seamlessly combined with the NS operation and simply realized by shift registers (SRs). The MSB CDEM reduces dominant in-band harmonic distortions due to capacitor mismatch by not only averaging out but also randomizing the MSB mismatch errors with modulation dither from the CIFF NS loop. In addition, a last-bit majority voting (LMV) technique is applied when resolving the LSB to reduce the comparator noise by half with four additional cycles. With both the LMV and CDEM techniques enabled, the SNR and SNDR are enhanced to 73.3 and 72.3 dB, respectively. The ADC achieves an ENOB of$11.2-11.7$bits with a reconfigurable bandwidth of 10–50 kHz at a supply voltage of 0.6–1 V. The prototype ADC was fabricated using 28-nm CMOS technology, occupying an active area of 0.0575 mm2.

With the increasing computational demands of the neural networks, many hardware accelerators for the neural networks have been proposed. Such existing neural network accelerators often focus on popular neural network types such as convolutional neural networks (CNNs) and recurrent neural networks (RNNs); however, not much attention has been paid to attention mechanisms, an emerging neural network primitive that enables neural networks to retrieve most relevant information from a knowledge-base, external memory, or past states. The attention mechanism is widely adopted by many state-of-the-art neural networks for computer vision, natural language processing, and machine translation, and accounts for a large portion of total execution time. We observe today's practice of implementing this mechanism using matrix-vector multiplication is suboptimal as the attention mechanism is semantically a content-based search where a large portion of computations ends up not being used. Based on this observation, we design and architect A3, which accelerates attention mechanisms in neural networks with algorithmic approximation and hardware specialization. Our proposed accelerator achieves multiple orders of magnitude improvement in energy efficiency (performance/watt) as well as substantial speedup over the state-of-the-art conventional hardware.

In this article, a maximum-eye-tracking clock and data recovery (MET-CDR) circuits for minimum bit error rate (BER) are presented. The proposed CDR does not require a BER counter or an eye-opening monitor with any iterative procedure to find the optimal sampling phase. The biased data level obtained from the weighted sum of error sampler outputs provides the actual eye height (EH) information in the presence of precursor intersymbol interference (ISI). Two samplers operating on two slightly different timings detect the current EH and the polarity of the eye slope so that the CDR can track the maximum EH where the slope becomes zero. Measured results show that the sampling phase of the maximum EH and that of the minimum BER match well. A prototype receiver fabricated in 28-nm CMOS process operates at 26 Gb/s with an eye-opening of 0.25 unit interval (UI) and consumes 87 mW while equalizing 23.5 dB of loss at 13 GHz.

This article presents an energy-efficient voltage-mode transmitter with an unsegmented output driver that equalizes channel loss in the time domain based on the phase delay analysis. By modulating the phase of the transmitting clock rather than the serialized data stream, the proposed transmitter significantly reduces data-dependent jitter. The horizontal eye opening is improved by compensating for the zero-crossing time variation dependent on the run length of the transmitted data. The proposed scheme significantly reduces the driver complexity by eliminating many driver slices that consume large signaling and switching power. The prototype chip has been fabricated in a 28-nm CMOS process and occupies an active area of 0.045 mm2. The measured results show that the proposed transmitter achieves an energy efficiency of 0.95 pJ/b at 22 Gb/s with an output swing of 440 mVppdat 1.0-V supply. In addition, peak-to-peak jitter is reduced from 34 to 20 ps at 22 Gb/s with the proposed phase delay compensation over the channel with a 15.0-dB loss.

A novel self-capacitance transition sensing method is presented for low-power touch detection using a capacitive touch-screen. While maintaining a voltage level, an additional electric charge is additionally required when a touch-input is newly added; the amount of charge is used for detection. Accordingly, the proposed current mirroring voltage-level regulation (CM-VLR) circuit senses the transition of self-capacitance of the touch-screen and detects motions of the touch-object. Only one CM-VLR cell is used to scan the entire touch-screen. Thus low-power readout and high integrated-circuit area efficiency are achieved. Moreover, the proposed self-capacitance sensing method does not require an offset-calibration step through a charge-sharing-based voltage generation and the offset-coverage capacitor. Fabricated in a 180-nm CMOS process, and the CM-VLR cell occupies 0.12 mm2. At a 120-Hz report rate, the proposed analog front-end (AFE) detects touch-input at a 32-dB SNR while dissipating 2.1 mW.

The price and power consumption of standard HDMI cables exponentially rise when the data rate increases or cable runs longer. HDMI active optical cable (AOC) can potentially solve price and power issues since fibers are tolerant to loss. However, additional optical components such as vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) are required. Therefore, drivers and transimpedance amplifiers should be designed carefully for normal operations. In this paper, two types of 4-channel VCSEL drivers for HDMI AOC are presented. The first type of the driver passes data and bias separately. It uses off-chip capacitors for AC coupling. On the other hand, the second type of the driver passes data including DC value without using off-chip capacitors. Structures of the both drivers are based on push-pull current-mode logic (CML) to achieve better power efficiency. Drivers fabricated in 0.18-μm CMOS process consume 36.5 mW/channel at 6 Gb/s and 24.7 mW/channel at 12 Gb/s, respectively.

A phase delay analysis is proposed against pursuing a flat group delay response for the design of wideband circuits. While it is believed that a large group delay variation introduces a large data-dependent jitter, this brief reconsiders the effectiveness of the group delay analysis in the evaluation of wideband circuits. Because of its own differentiating nature, the group delay provides a good insight on the delay variation at a vicinity of a certain frequency. However, for certain kind of wideband circuits, the group delay analysis cannot provide a sufficient insight since much of useful information is lost or distorted during the differentiating operation. In this brief, the effectiveness of the phase delay analysis is investigated and comparison with a traditional group delay analysis is presented with a theoretical approach and through a few circuit examples.

An explosive growth in the number of IT devices connected to a central system requires massive growth in aggregate bandwidth of wireline communications. As a result, a multi channel architecture is necessary in the high-speed I/O link to meet the ever increasing bandwidth requirement. Forwarded clock (FC) architecture offers the most efficient solution for the multi-channel I/O owing to the shared overhead of the additional clock channel. In this work, a power and area efficient FC transmitter (TX) is presented, in addition to a FC receiver (RX) previously presented by the authors in [1], The proposed FC TX provides a scalable data rate, output swing, and pre-emphasis without disturbing the output impedance.

A 800-Mb/s optical receiver based on pulse-position-modulation (PPM) scheme is presented. The proposed PPM receiver can recover the clock without any help of a reference clock or a forwarded clock. As a result, the number of wire and pin count is minimized. Moreover, the proposed receiver employs optical front-end circuits for fiber-optic communications which is optimized for low-power operation. The clock and data recovery (CDR) circuit is implemented with only a PLL and a sampling flip-flop to minimize the power consumption of the proposed receiver. A prototype chip is fabricated in 65-nm CMOS technology and dissipate s 711 μW at 800-Mb/s data rate, achieving the power efficiency of 0.89 pJ/b. The measured jitter tracking bandwidth of the prop osed receiver is about 10 MHz and the receiver sensitivity is measured to be -9.7 dBm for the BER of 10-12.

In this paper, the amount of phase shift with result of the pulse injection is derived mathematically and verified by simulation. The resultant phase shift is proportional to injection pulse width, and inversely proportional to on-resistance of the switch and total capacitance parallel to injection transistor. In addition, phase shift has sinusoidal form with two times the oscillation frequency. Furthermore, locking range can be estimated using the amount of the maximum resultant phase shift. Thereby, it is verified that pulse injection-locked oscillators using shorting scheme have two locking points in one period.

This paper describes a design methodology for CMOS silicon photonic interconnect ICs according to CMOS technology scaling. As the CMOS process is scaled, the endurable voltage stress and the intrinsic gain of the CMOS devices are reduced; therefore, a design of the highswing transmitter and high-gain receiver required at the silicon photonic interface becomes much more challenging. In this paper, a triple-stacked Mach-Zehnder modulator driver and an inverter-based transimpedance amplifier with inductive feedback are proposed, and the robustness of the proposed designs is verified through Monte Carlo analyses. The prototype ICs are fabricated using a 65-nm CMOS technology. The transmitter exhibits a 6 Vpp output swing, 98-mW power consumption, and 0.04-mm2active area at 10 Gb/s. The receiver was verified with a commercial photodetector, and it exhibits a 78-dBΩ gain, 25.3-mW power consumption, and 0.18-mm2active area at 20 Gb/s.

This paper presents a design of a pulse position modulation (PPM) transceiver. The proposed PPM receiver does not need clock forwarding or a reference clock. Moreover, the proposed receiver is implemented with a phase-locked loop and only a sampling flip-flop because need for a frequency detection circuit is eliminated. The duty-cycle distortions of the TX and RX clocks are tolerated without duty-cycle error correction. As a result, wire count and power consumption are minimized in the proposed transceiver. The proposed PPM transceiver is fabricated in 65-nm low-power CMOS technology, and dissipates 7 mW at 800-Mbps data rate. The proposed transceiver occupies a silicon area of 1.2 mm2. RMS jitter of the RX recovered clock is measured to 19.7 ps with PRBS-7 data pattern. The overall transceiver achieves an error-free operation.

An optical transmitter for driving a Mach-Zehnder (MZ) Interferometer is proposed which incorporates an alldigital phase-locked loop (ADPLL) and a source-series terminated (SST) driver. The proposed optical transmitter is composed of a pattern generator, a clock synthesizer and a modulator driver. The transmitter for an external modulator should drive a large capacitance with a high voltage swing, which requires both large power consumption and area. In this work, the ADPLL is employed for the clock synthesizer to achieve a small area and low power consumption. A high voltage swing over 2 Vdiff-ppwith low power is obtained by adopting the SST driver. The implemented transmitter occupies only 0.58 mm2with power dissipation of 391.6 mW at operating data rate of 21.6 Gb/s.

A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm2and consumes 22.1 mW at the data rate of 10 Gb/s.

A 20 Gb/s source-series-terminated (SST) driver that provides large output swing for optical modulator is presented. This work incorporates a stacked SST driver to enlarge output swing up to 3.6 VPP, Diff. For high-speed operation over 20 Gb/s, the stacked SST driver is implemented with only thin-oxide devices. In addition, a 2-tap feed-forward equalizer (FFE) is employed to offer pre-emphasis that can compensate non-ideal effects in the optical modulator or interconnection. The prototype is fabricated in 65-nm CMOS process. Electrical measurement results show that the proposed driver achieves 3.6 VPP, Diffoutput swing at 20 Gb/s. The power consumption of the prototype is 477 mW with 1.2 V and 2.4 V dual supplies. The prototype occupies 0.24-mm2active area.

This paper presents a design of an area-efficient 10-GHz PLL for source-synchronous, multi-channel applications. To be applied in the multi-channel application, the proposed PLL is implemented without use of any high-cost inductor to minimize silicon area while achieving 10-GHz operation frequency. A modified CML type ring-VCO is used to make the VCO outputs have consistent signal amplitude. The proposed PLL is fabricated in 90-nm low-power CMOS technology. The prototype IC occupies 0.075mm2of active area and dissipates 87.6-mW power from 1.2-V supply including a 10-GHz clock driver.

This paper describes a CMOS interface circuit for silicon photonics. 20-Gb/s operation of an optical receiver front-end circuit is demonstrated using an optical signal applied to the optical front-end. The transimpedance amplifier (TIA) is based on an inverter with resistive and inductive feedback for low power consumption and frequency compensation. A negative capacitance generation is employed in the limiting amplifier (LA) for bandwidth extension. The combined TIA and LA block exhibits a transimpedance gain of 78 dBΩ and a bandwidth of 11 GHz. The TIA and the LA block consume 1.3 mA and 24 mA at 1 V supply voltage, respectively.

A 10-Gb/s 6-Vppdifferential Mach-Zehnder modulator driver is implemented in 65-nm CMOS technology. The proposed modulator driver adopts a triple-stacking topology with a dynamic biasing to generate the differential voltage swing of six times as much as the nominal supply. The modulator driver occupies only 0.04 mm2without using inductors for area efficiency. The measurement results show an operating speed up to 10 Gb/s when electrically measured. The power consumption of this modulator driver is 98 mW which is lower than that of other modulator drivers exhibiting more than 6-Vppswing.

A phase-dependent gain-transition correlated double-sampling technique is proposed and applied to a 10-bit 75-MS/s pipelined analog-to-digital converter. This reduces the accumulation of predictive error of each multiplying digital-to-analog converter stage due to the finite gain of the operational amplifiers, without the need for additional capacitors and switches at the input. With a 10-MHz sinusoidal input, a prototype fabricated in a 0.13- μm CMOS process has a 56.90 dB signal-to-noise plus distortion ratio (SNDR) and a 64.57 dB spurious-free dynamic range (SFDR) at 75 MS/s. For a 37 MHz input at full sampling rate, the SNDR and SFDR are 55.01 and 60.77 dB, respectively. The IC has an active area of 0.65 mm2and consumes 32 mW with a 1.2 V supply.

A multichannel clock and data recovery (CDR) circuit that employs binary phase detectors (PDs) yet achieves linear loop dynamics is presented. The proposed CDR recovers the linear information of phase errors by exploiting its collaborative timing recovery architecture. Since the collaborative CDR combines the PD outputs of the multiple data streams, a deliberate phase offset can be added to each PD to realize a high-rate oversampling PD without additional PDs. The analysis shows that there exists an optimal spacing between these deliberate phase offsets that maximizes the linearity of the proposed PD for given jitter conditions. Under these conditions, the loop dynamics of a linear, second-order CDR model agree well with the simulated responses even with a finite latency difference between the proportional and integral control paths. The linearized characteristics of the PD and the overall CDR designed for 45-nm CMOS technology are, respectively, verified by using a time-step accurate behavioral simulation.

In this work, a 12.5-Gb/s trans-impedance amplifier (TIA) with capacitive peaking, limiting amplifier (LA) based on the Cherry-Hooper amplifier, and high-voltage laser/modulator driver are proposed in 0.13-μm CMOS process. The TIA and the LA operate without any inductors, and the TIA achieves a trans-impedance gain of 52.9-dBΩ and a bandwidth of 14.3GHz. The TIA and the LA use the negative Miller effect to extend the bandwidth without using any inductors. The core layout occupies an area of only 35*150 μm2. The laser/modulator driver of the transmitter drives the capacitance of the Mach-Zehnder modulator which contributes around 1.2pF. Using only thin MOS devices, the output swing of the driver exceeds 2.4V. The measurement results show the overall operating speed of 12.5-Gb/s.

A model-first flow is demonstrated for designing and validating a high-speed serial receiver in a digital TV. Starting with a functional model of the top-level mixed-signal system rather than with transistor-level designs helps detect problems due to the increasing interaction between the analog and digital circuits. Once the functionality of the system model is verified, the model can be leveraged as the specification for generating and validating the circuit and physical implementations of the system, automating a large portion of the design process.

Power gating in circuits is one of the effective technologies to allow low leakage and high performance operations. The key design considerations in the power mode transitions of power gating technology are minimizing the wakeup delay (for achieving high performance), the peak current (for reducing power supply/ground noise), and the total size of sleep transistors (for reducing area/design complexity). This work aims to analyze and establish the relations between the three important design parameters: 1) the maximum current flowing from/to power/ground; 2) the wakeup (sleep to active mode transition) delay; and 3) the total size of sleep transistors. With the understanding of relations between the parameters, we propose solution to the problem of finding logic clusters and their wakeup schedule that minimize the wakeup delay while satisfying the peak current constraint in wakeup time and performance loss constraint in normal operation. Specifically, we solve the problem by formulating it into repeated (incremental) applications of finding a maximum clique in a graph. From the experiments using ISCAS benchmarks, it is shown that our proposed technique is able to explore the search space, finding solutions with 71% and 30% reduced sizes of sleep transistors and 39% and 54% reduced wakeup delay, compared to the results by the previous work.

This paper presents an IEEE 1588-2008 adapter that provides existing Gigabit Ethernet equipment with the functionalities required to clock synchronization on the order of sub-microsecond. To compensate the time error caused by the queuing delays in the Gigabit Ethernet equipment, the adapter measures the residence time and runs the peer delay mechanism for the equipment. Major functional blocks including the clock synchronization cores, Media Access Controls (MACs), and frame buffers have been integrated into a 21 mm2silicon chip in 0.18 μm CMOS process. Experimental results show that the end devices can be synchronized within ±20 ns by simply attaching the proposed IEEE 1588-2008 adapters to the ordinary switches that connects the end devices.

Power gating in circuits is one of the effective technologies to allow low leakage and high performance operations. This work aims to analyze and establish the relations between the three important design parameters in power gated circuits: (i) the maximum current flowing from/to power/ground (ii) the wakeup (sleep to active mode transition) time delay and (iii) the number of sleep transistors. With the understanding of relations between the parameters, we propose solutions to the two problems: (1) finding logic clusters and their wakeup schedule to minimize the sleep transistor overhead under the constraints of wakeup time and peak current and (2) finding logic clusters and their wakeup schedule to minimize the wakeup time under the constraints of peak current and the number of sleep transistors. From an experimentation using ISCAS benchmarks, it is shown that our proposed technique is able to explore the search space, finding solutions with 65% ∼ 77% reduced number of sleep transistors and 30% ∼ 36% reduced wakeup time delay, compared to the results by the previous work.

An enhanced traffic policer capable of adaptive rate control to provide fair distribution of available network bandwidth is proposed. The policer also performs maximum rate control, limiting flow's use of network resources within a pre-defined bound. Since the enhanced policer is based on a token bucket policer, a flow is guaranteed to receive service at its reserved rate. The proposed policer partially employs a reduced fair queuing algorithm, which is designed for adaptive rate control based on the perceived traffic congestion level. The adaptive rate control requires measurement of the congestion level, which is approximated through examination of local buffer usage. As a result, the allocated service rate increase provided to the flows by the policer is inversely proportional to the network congestion level. In addition, far-travelling flows in multi-hop networks receive the same service rate enhancements as short-travelling flows. The proposed scheme is useful in Ethernet networks, especially access networks, where quality of service is not well organised.

In this paper, we describe the design and implementation of OTCA (ownership-tagged cell allocation) MAC protocol for a unidirectional slotted ring network with a distributed fair medium access. A point-to-point (p2p) interconnection network in a ring topology with a high-speed serial link and the sharing of network bandwidth among multiple communicating nodes offers a very promising low cost solution in the growing gigabit communication system, where it is a challenge to run high quality real-time multimedia. Some services have explicit timing requirements. The OTCA MAC protocol provides the deterministic network behavior guaranteeing the worst latency bound and the minimum bandwidth availability. On a 1.063 Gpbs p2p ring network comprising 4 nodes, the OTCA MAC protocol ensures a bandwidth of 265 Mbps for synchronous data, 232 Mbps for asynchronous data (thus a total of 497 Mbps for a mode), and the worst medium access latency is bounded with 17.46 us.

This paper proposes a cost-effective solution to the synonym problem. In this proposed solution, a minimal hardware addition guarantees the correctness whereas the software counterpart helps improve the performance. The key to this proposed solution is an addition of a small physically-indexed cache called U-cache. The U-cache maintains the reverse translation information of the cache blocks that belong to un-aligned virtual pages only, where aligned means that the lower bits of the virtual page number match those of the corresponding physical page number. A U-cache, even with only one entry, ensures correct handling of synonyms. A simple software optimization in the form of page alignment, helps improve the performance. Performance evaluation based on ATUM traces shows that a U-cache, with only a few entries, performs almost as well as (in some cases outperforms) a fully-configured hardware-based solution when more than 95% of the pages are aligned.>

A new approach to the design of sub-converter for use in a multibit /spl Delta/-/spl Sigma/ D/A converter is described. It uses a differential charge integrator to realize the S/N ratio of more than 75 dB without requiring precise matching among passive elements. The sub-converter was successfully fabricated in a 1.5-/spl mu/m CMOS technology. Measured results show 65-dB S/(N+D) ratio with an oversampling ratio of 32.>