Yan Xue

dblp:12/1743 · DBLP profile ↗
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12ranked-venue papers
5as first author
9since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 6 · 2 first-author · 5 since 2021Systems, architecture and hardware · 4 · 3 since 2021Computer networks · 2 · 2 first-authorDatabases, data management, data science and information retrieval · 2 · 2 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2026 Chain-of-Thought Prompting for Frame Identification with Large Language Models
Xuefei Cao, Yan Xue, Ruibo Wang
KSEM (6)3
2026 A calibration technology for SAR ADC with PGA based on poly resistor linearization and sampling capacitance bit-weight mismatch
Wei Sheng, Jiashen Li, Yan Xue, Mingyuan Ye, Yongsheng Yin
Integr.4
2025 An OTA with Series-Cascode-Miller Compensation and Anti-Pole-Splitting for a 360-MHz BW Low-Distortion TIA in Sub-6G Broadband RF Receivers
abstract
This paper presents a fully differential 2-stage operational transconductance amplifier (OTA) for a baseband transimpedance amplifier (TIA) with 360-MHz bandwidth (BW) aiming for applications in Sub-6G broadband direct-conversion receivers. The proposed OTA with folded-cascode input stage incorporates three techniques, including series-cascode-Miller compensation (SCMC), anti-pole-splitting path, and common-mode feedforward (CMFF) to ensure wideband and low distortion of the TIA with shunt feedback. The OTA’s BW is extended because the SCMC introduces a zero that cancels the non-dominant pole at the folding node of the OTA, while the anti-pole-splitting path generates a negative capacitance that neutralizes the parasitic capacitance. In addition, the CMFF circuit improves the OTA’s common-mode rejection ratio (CMRR) by about 20 dB. Designed in 28-nm CMOS with a 0.12-mm2layout area and 16.6-mW power consumption, the TIA demonstrates an SFDR of 103 dB for a 75-MHz, 250-mVpp output, an input-referred noise (IRN) of 85 µVrms, an in-band third-order input intercept point (IIP3) of 37.9 dBm, and an intermodulation-free dynamic range (IMFDR3) of 91.6 dB.
Junyao Ji, Yan Xue, Xiaojie Fan, Youxiang Chen, Ruibai You
ISCAS2
2025 Bayesian Model Comparison Based on Cross-Validated Estimation of F1 Measure
Yan Xue, Xuefei Cao, Xingli Yang, Jihong Li
PRCV (1)1
2025 Model Evaluation with Precision, Recall, and F1 Measure Based on Block-regularized m×2 Cross Validation for Text Corpus
Yan Xue, Xuefei Cao, Xingli Yang, Jihong Li
PRICAI (4)1
2024 Artificial Neural Network Based Calibration for a 12 b 250 MS/s Pipelined-SAR ADC With Ring Amplifier in 40-nm CMOS
abstract
This paper presents a 2-stage pipelined-SAR ADC with artificial-neural-network (ANN) based digital calibration algorithm to calibrate the mismatch error in the$1^{\mathrm {st}}$-stage capacitive DAC (CDAC) and the inter-stage gain error (IGE) together. Previous ANN-based calibration schemes suffer from excessive power and hardware overhead due to the large number of network parameters. To facilitate hardware implementation, the proposed algorithm only requires$N_{1}+1$input parameters ($N_{1}$is the resolution of the$1^{\mathrm {st}}$-stage SAR ADC), in which the overall output of the$2^{\mathrm {nd}}$-stage SAR ADC is combined into a single parameter. In addition, the ANN utilizes a single-neuron hidden layer with linear activation function to calculate the actual bit weight of the ADC, remarkably reducing the hardware overhead and power consumption of the calibration circuit. The prototype 12-bit, 250 MS/s pipelined-SAR ADC with “loop-unrolled” architecture is implemented in 40-nm CMOS, in which a ring amplifier with improved bias circuit is used to realize a robust closed-loop gain for residue amplification. With the ANN-based calibration circuit implemented in an FPGA, the calibrated ADC achieves the SNDR of 65.0 dB and the SFDR of 84.0 dB at Nyquist input (124 MHz), with a Schreier figure of merit of 169.0 dB and a Walden figure of merit of 14.0 fJ/conv-step. The ADC core consumes 4.95 mW, with an active area of only 0.013 mm2.
Bin Liu 0068, Zhichao Dai, Yufeng Ge, Huanhuan Qi, Jie Zhang 0039, Zhenhai Chen, Yan Xue, Hong Zhang 0009
IEEE Trans. Circuits Syst. I Regul. Pap.12
2023 We Need to Talk About Reproducibility in NLP Model Comparison
abstract
NLPers frequently face reproducibility crisis in a comparison of various models of a realworld NLP task.Many studies have empirically showed that the standard splits tend to produce low reproducible and unreliable conclusions, and they attempted to improve the splits by using more random repetitions.However, the improvement on the reproducibility in a comparison of NLP models is limited attributed to a lack of investigation on the relationship between the reproducibility and the estimator induced by a splitting strategy.In this paper, we formulate the reproducibility in a model comparison into a probabilistic function with regard to a conclusion.Furthermore, we theoretically illustrate that the reproducibility is qualitatively dominated by the signal-tonoise ratio (SNR) of a model performance estimator obtained on a corpus splitting strategy.Specifically, a higher value of the SNR of an estimator probably indicates a better reproducibility.On the basis of the theoretical motivations, we develop a novel mixture estimator of the performance of an NLP model with a regularized corpus splitting strategy based on a blocked 3 × 2 cross-validation.We conduct numerical experiments on multiple NLP tasks to show that the proposed estimator achieves a high SNR, and it substantially increases the reproducibility.Therefore, we recommend the NLP practitioners to use the proposed method to compare NLP models instead of the methods based on the widely-used standard splits and the random splits with multiple repetitions.
Yan Xue, Xuefei Cao, Xingli Yang, Yu Wang 0092, Ruibo Wang, Jihong Li
EMNLP1
2023 An Improved Cross-Validated Adversarial Validation Method
Zhengjiang Liu, Yan Xue, Ruibo Wang, Xuefei Cao, Jihong Li
KSEM (1)3
2023 Dynamic model averaging-based procurement optimization of prefabricated components
Juan Du 0004, Xiufang Li, Vijayan Sugumaran, Yuqing Hu 0002, Yan Xue
Neural Comput. Appl.5
2016 Primary user activity prediction based joint topology control and stable routing in mobile cognitive networks
abstract
The stability of links in mobile cognitive networks (MCNets) is significantly affected by primary user activities and node mobility, which makes topology control and stable routing more challenging than that in traditional wireless networks. In multi-channel multi-hop MCNets, it will become worse. In this paper, we propose a primary user activity prediction model to reveal channel utilization patterns of primary users. Next, we put forward a novel routing metric Primary user activity Prediction based Stability Metric (PPSM) to quantitatively capture the affect of primary user activities and node mobility. Finally, we propose and implement a Primary user activity Prediction based Joint Topology Control and Stable Routing (PP-JTCSR) protocol for maximizing network throughput based on our primary user activity prediction model, which can find out the most stable and the shortest path between a source and a destination. NS2-based simulation results demonstrate that our PP-JTCSR protocol can generate stable topology through predicting link and path duration quantitatively, and outperforms related proposals in terms of path stability and average throughput.
Yan Xue, Can Tang, Feilong Tang 0001, Yanqin Yang, Jie Li 0002, Minyi Guo, Jinsong Wu 0001
WCNC1
2012 Transport Performance Optimization Based on Network Coding in WMN
abstract
When network coding is adopted to optimize transport performance of WMN networks, it has problems such as end to end delay and compatibility with wireless network environment emerge. With this in mind, this paper explores transport technologies based on network coding and TCP Reno protocol and reveals these problems by simulations. End to end delay optimized method is proposed based on optimal block size of file transported. And an automatic tuning method for the redundancy factor R is also proposed based on congestion detection and link quality detection. Performance of all these contributions is evaluated by simulation results.
Yan Xue, Sanfeng Zhang 0002, Di Huang 0004
MSN1
2006 Advanced Animation Engine for User-Interface Robots
abstract
This paper describes an improved animation system for user-interface robots. The animation system is based on the animation engine presented by van Breemen, A.J.N. (2004), and uses animation channels for playing and blending multiple animations concurrently. The presented improvement is twofold. First, this paper describes an extension to the computational structure of an animation channel. A fading mechanism is added to an animation channel in order to realize a smooth transition from one animation to another. Secondly, this paper explains how to setup animations for a user-interface robot application. A technique based on behavior mode animations and action animations is described for this. The animation system has been implemented and tested using the Philips iCat Research Platform
Albert J. N. van Breemen, Yan Xue
IROS2