G. K. Rosendahl

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1ranked-venue papers

0as first author

0since 2021 · last 1998

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems 1 paper		Reconfigurable computing and FPGAs · 50% Hardware accelerators and domain-specific architectures · 50%
Artificial intelligence 1 paper		Representation and self-supervised learning · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator neural network accelerator	1	1998	Competitive Learning Algorithms and Neurocomputer Architecture · IEEE Trans. Computers 1998
Machine learning › Representation and self-supervised learning › prototype learning competitive learning	1	1998	Competitive Learning Algorithms and Neurocomputer Architecture · IEEE Trans. Computers 1998
Machine learning › Representation and self-supervised learning › prototype learning self-organizing map	1	1998	Competitive Learning Algorithms and Neurocomputer Architecture · IEEE Trans. Computers 1998

Methods — techniques the papers use, named apart from their topics

digital signal processing · 0.0broadcast network · 0.0FPGA · 0.0

Year	Publication	Venue	Position
1998	Competitive Learning Algorithms and Neurocomputer Architecture abstract This paper begins with an overview of several competitive learning algorithms in artificial neural networks, including self-organizing feature maps, focusing on properties of these algorithms important to hardware implementations. We then discuss previously reported digital implementations of these networks. Finally, we report a reconfigurable parallel neurocomputer architecture we have designed using digital signal processing chips and field-programmable gate array devices. Communications are based upon a broadcast network with FPGA-based message preprocessing and postprocessing. A small prototype of this system has been constructed and applied to competitive learning in self-organizing maps. This machine is able to model slowly-varying nonstationary data in real time. Howard C. Card, G. K. Rosendahl, Dean K. McNeill, Robert D. McLeod	IEEE Trans. Computers	2