Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

C. A. Looby

dblp:12/2463 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 70% Reconfigurable computing and FPGAs · 30%

Topics — the 2 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.011997
A CMOS Continuous-Time Field Programmable Analog Array · FPGA 1997
Integrated circuit design › analog and mixed-signal circuits › analog VLSI
field programmable analog array
0.011997
A CMOS Continuous-Time Field Programmable Analog Array · FPGA 1997

Methods — techniques the papers use, named apart from their topics

op-amp based function blocks · 0.0CMOS switches · 0.0
YearPublicationVenuePosition
1997 A CMOS Continuous-Time Field Programmable Analog Array
abstract
A circuit design for a Field Programmable Analog Array is presented which improves accuracy and repeatability compared to previous designs. Controlled by a configuration register, continuous-time signals are routed among programmable analog blocks to implement the user's chosen circuit. The configurable connections are realized by CMOS switches and a new innovation is that these are either buffered or nulled to cancel parasitic error. The function blocks are Op-Amps combined with passive networks which allow programmable transfer functions with accuracy insensitive to variations in process parameters and environment. The intended application area is the rapid development of analog circuits which are presently prototyped by PCBs stuffed with Op-Amp and passive components. The concept has been demonstrated on a CMOS IC and the resulting performance shows the feasibility of this approach to general purpose FPAA technology.
C. A. Looby, Colin Lyden
FPGA1