The tradeoff between visualizing or hiding the highest levels of the memory hierarchy, which impacts both performance and scalability, is examined by comparing a set of architectures from three major architecture families: stack, register, and memory-to-memory. The stack architecture is used as reference. It is shown that scalable architectures require at least 32 words of local memory and therefore are not applicable for low-density technologies. It is also shown that software support can bridge the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local storage allocated interprocedurally outperforms scalable architectures with equal sized local memories and even some with larger sized local memories. When a small cache is added to an unscalable architecture, their performance advantage becomes significant.>

Article Software pipelining for transport-triggered architectures Share on Authors: Jan Hoogerbrugge Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital Systems Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital SystemsView Profile , Henk Corporaal Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital Systems Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital SystemsView Profile , Hans Mulder Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital Systems Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital SystemsView Profile Authors Info & Claims MICRO 24: Proceedings of the 24th annual international symposium on MicroarchitectureSeptember 1991 Pages 74–81https://doi.org/10.1145/123465.123479Online:01 September 1991Publication History 12citation319DownloadsMetricsTotal Citations12Total Downloads319Last 12 Months4Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

CPU architectures allowing exploitation of instruct ion-level par­ allelism (pipelining, VllW, supersc alar) exhibit poor average hardware utilization and complex hardware organizations. We propose a different architecture with a less complex hardware or­ ganization and significantly better hardware utilization. This ar­ chitecture allows short cycle implementations, and is easily con­ figurable in functionality and scalable in performance. Besides being suitable for high-performance general-purpose computing, the architecture is particularly useful as framework for the (semi) automaJic generation of high-performance processo rsfor specific applications. The key feature of this architecture is the separation of data trans­ port and data operations. This separation yields a degree of auto­ nomicity for the different operational units which allows,for exam­ ple, diff erent units to implement different pipelining schemes. Fur­ thermore this separation allows the machine cycle to be reduced to the transport delay. The resulting programming model is quite unusual and provides scheduling possibilities unexploitable in the aforementioned architectures. We believe this architecture will be a favorable candidaJe for future powerful computing systems.

Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).

Two major limitations concerning the design of cost-efective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture. The, Scalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling Of functionality, implementation complexity, and performance. The SCARCE framework con- sists and will consist Of: an architecture framework defirting the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick gener- ation of application-specific processors; a system-software plat- form which can be retargeted quickly to fit the application- specific architecture; This paper concentrates primarily on the architecture frame- work of SCARCE, but also presents briefly some software issues and outlines the process of generating VLSI processors.