With the progress in hardware implementation of artificial neural networks, the ability to analyze their faulty behavior has become increasingly important to their diagnosis, repair, reconfiguration, and reliable application. The behavior of feedforward neural networks with hard limiting activation function under stuck-at faults is studied in this article. It is shown that the stuck-at-M faults have a larger effect on the network's performance than the mixed stuck-at faults, which in turn have a larger effect than that of stuck-at-0 faults. Furthermore, the fault-tolerant ability of the network decreases with the increase of its size for the same percentage of faulty interconnections. The results of our analysis are validated by Monte-Carlo simulations.

We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model.Our algorithms represent a departure f r om previous approaches in that we derive an explicit area/delay tradeo curve.We achieve this goal by limiting the solution space to the set of topologies induced b y a p ermutation on the sinks of the net.This constraint allows ecient identi cation of optimal solutions while still providing a rich solution space.We also incorporate simultaneous wire sizing.Our technique consistently p r o duces topologies equalling the performance o f previous approaches with substantially less area overhead.

Pseudo-exhaustive testing (PET) offers a simple solution to testing complex circuits and systems [12].However, PET suffers long testing time for test generation and high area overhead of test hardware.The pipelined pseudo-exhaustive testing (PPET) achieves fast testing time with high fault coverage by pipelining test vectors and test responses among partitioned circuit segments [15].To reduce hardware overhead in PPET, a novel approach for implementing area-efficient PPET is presented.Circuit partitioning with retiming is used to convert designs for PPET.Experimental results show that this approach exhibits an average of 20% area reduction over non-retimed testable circuits.Our algorithm offers high utilization of existing flip-flops (FFs) and provides a framework for further performance optimization.

We present an algorithm for simultaneously finding a rectilinear Steiner tree T and buffer insertion points into T. The objective of the algorithm is to minimize a cost function (e.g., total area or power) subject to given timing constraints on the sinks of the net. An interesting side-effect of our approach is that we are able to derive an entire cost/delay tradeoff curve for added flexibility. The solutions produced by the algorithm are optimal subject to the constraint that the routing topology be induced by a permutation on the sinks of the net. We show that high quality sink permutations can be derived from a given routing structure such as the minimum spanning tree. This derivation provides an error bound on the minimum area solution induced by the permutation. The effectiveness of our algorithm is demonstrated experimentally.

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We present efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion. Our algorithms are able to minimize dynamic power dissipation subject to given timing constraints. In addition, we compute the complete power-delay tradeoff curve for added flexibility. We extend our algorithm to take into account the effect of signal slew on buffer delay which can contribute substantially to overall delay. The effectiveness of these methods is demonstrated experimentally.

Recently, Johnson et al. [1989] presented an excellent comparison of simulated annealing and Kernighan-Lin algorithms. However, their test beds were limited to random and geometric graphs. We present a complete evaluation by adding real circuitry into the test beds. A two-level partitioning algorithm called the primal-dual algorithm is also incorporated for comparison. We show that at least 500 runs are necessary to demonstrate the performance of the Fiduccia-Mattheyses algorithm, whereas traditional way of evaluation tends to underestimate. Nevertheless, our new results show that for two-way partitioning on real circuits, the primal-dual algorithm is, in general, a better choice than both the Fiduccia-Mattheyses algorithm and the simulated annealing algorithm. This conclusion is more likely to hold when the primal-dual algorithm is switched to a simpler mode.>

We present a new clustering metric, based on a random graph model and a ratio cut concept. The minimization of the proposed clustering cost can be transformed to a uniform multicommodity flow problem by adding artificial weight functions, which can be solved by a multicommodity flow-based algorithm with high complexity. We devise a probabilistic flow injection approach which drastically reduces the complexity of the flow-based algorithm. Experimental results show that this algorithm generates promising results with respect to the proposed metric.>

Multiple-way partitioning is an important extension of two-way partitioning as it provides a more natural and direct model for many partitioning applications. In this paper, we discuss several objective functions derived from such an extension and propose an iterative improvement algorithm to solve the multiple-way partitioning problem. The algorithm proceeds in three phases. The first phase employs a recursive ratio-cut scheme to group highly connected subcircuits into clusters. The second phase performs iterative improvement on the clustered circuit using a Dew net-based move model and a Primal-Dual refinement procedure. The third phase is the same as the second phase except that the iterative improvement is done on the original circuit. Experiments show good results in all tested cases.>

Circuit clustering, which plays a fundamental role in hierarchical designs, is discussed. Identifying strongly connected components in the circuits can significantly reduce the complexity of the design and improve the performance of the design process. However, there has not been a clear objective function for circuit clustering. A clustering metric based on the random graph model and the ratio cust concept is presented. A probabilistic, multicommodity flow based algorithm is proposed and tested under the clustering metric. Experimental results show that this algorithm generates promising results with respect to the proposed metric. Extensions and directions for future work are also proposed.>

This paper presents a discussion of methods to solve multiple way partitioning problems under three different objective functions.A multicommodity flow fzeatmertt is proposed for partitioning without a size wmstrain~and an iterative improvement algorithm is proposed for partitioning with a size comt.rstint.This algoriti incorporates a top-down clustering technique to deal with the local minima problems in common heuristics, a novel multi-pin net model to capture the contributory moves, and a Primal-Dual iteration to enhance the iterative improvement.Experiments show good results in all tested cases over the algorithm proposal in [12].Also, the effect of different objective functions is manifested through numerical tabulation.