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James Crabbe

dblp:12/4310 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1986
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 73% Energy-efficient computing · 21% Integrated circuit design · 6%

Topics — the 4 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.011986
HAPPI: a chip compiler based on double-level-metal technology · DAC 1986
Electronic design automation › physical design
placement
0.011986
HAPPI: a chip compiler based on double-level-metal technology · DAC 1986
Energy-efficient computing › power delivery
power distribution
0.011986
HAPPI: a chip compiler based on double-level-metal technology · DAC 1986
Electronic design automation › physical design
routing
0.011986
HAPPI: a chip compiler based on double-level-metal technology · DAC 1986

Methods — techniques the papers use, named apart from their topics

heuristic placement · 0.0double-level-metal technology · 0.0
YearPublicationVenuePosition
1986 HAPPI: a chip compiler based on double-level-metal technology
abstract
This paper describes a unique fully automatic chip compiler, HAPPI, that uses double-level-metal technology and 3 levels of interconnection to realize high-speed and maximum-density chip designs consisting of a varying mixture of custom and standard-cell macros within a chip topology that guarantees 100% signal and power routing. A heuristic technique for generating placements of “soft macros” that are balanced in both area and connectivity has been presented. A routing approach that uses three level interconnection to guarantee 100% signal routing at no more than maximum density +1 tracks for channels is described, as well as a method for distributing power inside the chip in two-level metal. Finally, results of chip design using the HAPPI compiler have been presented.
Rathin Putatunda, Stephen McNeary, James Crabbe
DAC4
1981 User documentation for Design Automation at TI
Diana Mae Sims, James Crabbe
DAC2