Intelligent reflecting surfaces (IRS) represent a groundbreaking technology that has redefined how propagation channels are envisioned in future wireless systems. In situations with significant signal blockage, the IRS can redirect transmitted signals to ensure that they reach the receiver. However, to fully benefit from the IRS, accurate knowledge of the channel between the transmitter and receiver via the IRS is essential, which is challenging because of the passive nature of the surface. Many IRS channel estimation algorithms are grounded in conventional least squares or minimum mean squared error algorithms, whose performance becomes questionable when the channel model deviates from Gaussian assumptions. This is one of the first papers to look at channel estimation for IRS-assisted multiuser multiple-input single-output (MISO) communication systems under impulsive noise using a robust cost function. Another significant challenge arises from the need for more transmit pilot symbols to achieve the same performance as in an additive white Gaussian noise (AWGN) channel, especially in impulsive noise environments. To mitigate this, we incorporate distributed optimization into the estimation process to jointly estimate the common BS-IRS channel with multiple users. The cascaded BS-IRS-user channel is estimated by alternately applying iteratively reweighted least squares (IRLS) estimation to the BS-IRS and IRS-user channels. The simulation results demonstrate the superior performance of the proposed algorithm in various impulsive noise environments.

The computation of inner products of any given pair of vectors is an indispensable requirement in several applications including artificial intelligence (AI), machine learning (ML), signal processing, image processing, communication, and many others. The throughput requirement of inner product computation varies widely for different applications. Moreover, the throughput of computation must match the requirements of the applications. It is therefore important to design flexible hardware for inner product computation that produces the desired throughput. Distributed arithmetic (DA) is a well-known approach for efficient inner product computation. This article presents an efficient DA-based architecture for computing the inner product of variable vectors, which could be tailored according to the throughput requirement of any given application and reused for different inner product lengths. The proposed designs could also be deployed to achieve a trade-off between throughput and area/energy consumption. In this article, we have used modified Booth encoding (MBE) to reduce the number of partial products and proposed a novel carry-save accumulator (CSA) for shortening the critical path delay. The proposed designs are synthesized by Cadence Genus using GPDK 90-nm technology library and place-and-route using Cadence Innovus for different inner product lengths and word lengths. As found from the postlayout synthesis results, the proposed designs offer savings of nearly 30% and 29% EPC and ADP over the bit-serial DA-based design on average for word lengths 8 and 16 and inner product lengths 8, 16, and 32, respectively.

Computation of the inner products is frequently used in machine learning (ML) algorithms apart from signal processing and communication applications. Distributed arithmetic (DA) has been frequently employed for area-time efficient inner-product implementations. In conventional DA-based architectures, one of the vectors is constant and known a priori. Hence, the traditional DA architectures are not suitable when both vectors are variable. However, computing the inner product of a pair of variable vectors is frequently used for matrix multiplication of various forms and convolutional neural networks. In this paper, we present a novel DA-based architecture for computing the inner product of variable vectors. To derive the proposed architecture, the inner product of any given length is decomposed into a set of short-length inner products, such that the inner product could be computed by successive accumulation of the results of short-length inner products. We have designed a DA-based architecture for the computation of the short-length inner-product of variable vectors and used that in successive clock cycles to compute the whole inner-product by successive accumulation. The post-layout synthesis results using Cadence Innovus with a GPDK 90nm technology library show that the proposed DA-based parallel architecture offers significant advantages in area-delay product and energy consumption over the bit-serial DA architecture.

Abstract This paper presents a multiplierless image-cipher, with extendable 2048-bit key-space, based on a 4-dimensional (4D) quantized piece-wise linear cat map (PWLCM). The quantized PWLCM exhibits limit-cycles of 4-bit encoded integers with periods greater than 107. The synthesis of the PWLCM in a finite state space allows to eliminate the undesirable finite precision effect due to the hardware realization. The proposed image-cipher combines chaos, modular arithmetic, and lattice-based cryptography to encrypt a color image by performing pixel permutation and diffusion in a single operation. Further, an image-dependent confusion operation based on an 8-bit 2D-PWLCM is performed on the whole image to enhance security. In order to increase the key-space without key duplication, 16 × 16 sub-images are modified using sub-keys of different lattice length vectors generated from the external key. Both simulations and security analyses confirm that the proposed algorithm can resist common cipher attacks, in addition to its advantages such as simplicity, ease of implementation on low-end processors and extensibility of key-space that allows it to easily adapt even for future post-quantum computing attacks.

Distributed arithmetic (DA) is generally used for area-time efficient implementation of inner products, where one of the vectors is fixed and known a priori. Therefore, the conventional DA architectures cannot be used when both vectors are variable. This article proposes a novel architecture for computing inner products of variable vectors, where one of the vectors is encoded using the radix-4 modified Booth technique to reduce the logic complexity. The proposed structure for inner-product computation consists of two sections. The first Section of the architecture performs a carry-save reduction of the partial-inner-products of the same weight to two words. During every successive clock cycle, it reduces such partial-inner-products of different weights in the order of the lowest to the highest weight. In the second Section of the architecture, the pair of reduced words produced by the first Section are shift accumulated. The area, delay, and power saving are achieved by reducing the overall critical path of the structure as well as the logic complexity in both sections. The proposed architecture is synthesized by Cadence Genus using TSMC 90-nm technology library and place-and-route using Cadence Innovus for different inner-product lengths and word lengths. The postlayout synthesis results show that the proposed DA-based architecture offers significant advantages in area-delay product (ADP) and energy per computation (EPC) over the radix-4 Booth multiplier-accumulator-based architectures.

Spectrum sensing is a key component to realise the cognitive radio. The main requirements of spectrum sensing are the prediction of signal status in multiple frequency bands in a low signal‐to‐noise ratio (SNR) and decision reliability. This study proposes a novel multinode wideband sensing technique to predict the status of multiple frequency bands based on the integration of entropy and cyclic properties of received signals. It uses the uncertainty and auto‐correlation properties of the deterministic signal and noise in the frequency domain for signal detection. To increase the decision reliability, cooperative sensing techniques are being used for spectrum sensing. Although cooperation among multiple cognitive users enhances the sensing performance, presence of few suspicious/malicious cognitive users severely degrade the decision reliability of the system. Hence, in this work, generalised extreme studentised deviate and adjusted box‐plot methods are introduced to eliminate multiple malicious users in the cooperation. The proposed sensing method shows the best performance and is less severe to noise uncertainties compared to the traditional sensing methods in the literature. It enhances the sensing performance by 2.5 dB using five nodes in cooperation for same sensing parameters compared to other detection methods. It is a significant improvement for IEEE 802.22 systems that work under low SNR environment.

Wireless Sensor Networks (WSNs) offer an excellent opportunity to monitor environments, and have a lot of interesting applications, some of which are quite sensitive in nature and require full proof secured environment. The security mechanisms used for wired networks cannot be directly used in sensor networks as there is no user-controlling of each individual node, wireless environment, and more importantly, scarce energy resources. In this paper, we address some of the special security threats and attacks in WSNs. We propose a scheme for detection of distributed sensor cloning attack and use of zero knowledge protocol (ZKP) for verifying the authenticity of the sender sensor nodes. The cloning attack is addressed by attaching a unique fingerprint to each node, that depends on the set of neighboring nodes and itself. The fingerprint is attached with every message a sensor node sends. The ZKP is used to ensure non transmission of crucial cryptographic information in the wireless network in order to avoid man-in-the middle (MITM) attack and replay attack. The paper presents a detailed analysis for various scenarios and also analyzes the performance and cryptographic strength.