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Wen Yujie

dblp:12/4585 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 62% Electronic design automation · 38%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA architecture
0.112005
Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only) · FPGA 2005
Electronic design automation › physical design › routing
FPGA routing
0.012005
Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only) · FPGA 2005
Electronic design automation › physical design › routing › FPGA routing
switch box design
0.012005
Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only) · FPGA 2005

Methods — techniques the papers use, named apart from their topics

placement and routing · 0.1benchmark circuit evaluation · 0.1
YearPublicationVenuePosition
2005 Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only)
abstract
Non-uniform routing architecture contains routing channels of different widths. In this paper we propose a design methodology of domain specific non-uniform programmable routing architecture for embedded programmable IP cores. This non-uniform architecture is based on symmetrical FPGA model and consists of connection boxes of full connectivity and rectangular switch boxes. The rectangular switch box is derived from universal switch box module. Area and timing efficiency of the proposed architecture is compared with those of uniform architecture based on placement and routing result over a set of MCNC benchmark circuits. The comparison results show that non-uniform routing architecture gains up to 8% layout area reduction from uniform ones. Besides, by widening some of the routing channels where routing congestions accumulate, the average critical path delay of non-uniform architecture is 8% less than that of uniform one while maintain the same area.
Wen Yujie, Jiarong Tong, Charles C. Chiang
FPGA1