Research in human–robot interaction for assistive robotics usually presents many technical challenges for experimenters, forcing researchers to split their time between solving technical problems and conducting experiments. In addition, previous work in virtual reality setups tends to focus on a single assistive robotics application. In order to alleviate these problems, we present ArmSym, a virtual reality laboratory with a fully simulated and developer-friendly robot arm. The system is intended as a testbed to run many sorts of experiments on human control of a robotic arm in a realistic environment, ranging from an upper limb prosthesis to a wheelchair-mounted robotic manipulator. To highlight the possibilities of this system, we perform a study comparing different sorts of prosthetic control types. Looking at nonimpaired subjects, we study different psychological metrics that evaluate the interaction of the user with the robot under different control conditions. Subjects report a perception of embodiment in the absence of realistic cutaneous touch, supporting previous studies in the topic. We also find interesting correlations between control and perceived ease of use. Overall our results confirm that ArmSym can be used to gather data from immersive experiences prosthetics, opening the door to closer collaboration between device engineers and experience designers in the future.

A brain-computer interface (BCI) is used to enable communication between humans and machines by decoding elicited brain activity patterns. However, these patterns have been found to vary across subjects or even for the same subject across sessions. Such problems render the performance of a BCI highly specific to subjects, requiring expensive and time-consuming individual calibration sessions to adapt BCI systems to new subjects. This work tackles the aforementioned problem in a Bayesian multi-task learning (MTL) framework to transfer common knowledge across subjects and sessions for the adaptation of a BCI to new subjects. In particular, a recent framework, that is able to exploit the structure of multi-channel electroencephalography (EEG), is extended by a Bayesian hierarchical logistic regression decoder for probabilistic binary classification. The derived model is able to explicitly learn spatial and spectral features, therefore making it further applicable for identification, analysis and evaluation of paradigm characteristics without relying on expert knowledge. An offline experiment with the new decoder shows a significant improvement in performance on calibration-free decoding compared to previous MTL approaches for rule adaptation and uninformed models while also outperforming them as soon as subject-specific data becomes available. We further demonstrate the ability of the model to identify relevant topographies along with signal band-power features that agree with neurophysiological properties of a common sensorimotor rhythm paradigm.

Brain-computer interfaces (BCIs) are often based on the control of sensor motor processes, yet sensor motor processes are impaired in patients suffering from amyotrophic lateral sclerosis (ALS). We devised a new paradigm that targets higher level cognitive processes to transmit information from the user to the BCI. We instructed five ALS patients and eleven healthy subjects to either activate self-referential memories or to focus on processes without mnemonic content, while recording a high density electroencephalogram (EEG). Both tasks are likely to modulate activity in the default mode network (DMN) without involving sensor motor pathways. We find that the two tasks can be distinguished from band power modulations in the theta (3 -- 7 Hz) and alpha-range (8 -- 13 Hz) in fronto-parietal areas, consistent with modulation of neural activity in primary nodes of the DMN. Training a support vector machine (SVM) to discriminate the two tasks on theta- and alpha-power in the precuneus, as estimated by a beam forming procedure, resulted in above chance-level decoding accuracy after only one experimental session. Therefore, the presented work could serve as a basis for a novel tool which allows for simple, reliable communication with patients in late stages of ALS.

Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise is increasing. The supply noise is much larger during at-speed delay test compared to normal circuit operation since large number of transitions occur within a short time frame. Existing commercial ATPG tools do not consider the excessive supply noise that might occur in the design during test pattern generation. In this paper, we first present a case study of a SOC design and show detailed IR-drop analysis, measurement and its effects on design performance during at-speed test. We then propose a novel method to measure the average power of at-speed test patterns, referred to as switching cycle average power (SCAP). A new practical pattern generation methodology is proposed to generate supply noise tolerant delay test patterns using existing capabilities in commercial ATPG tools. The results demonstrate that the new patterns generated using our technique will minimize the supply noise effects on path delay.

The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The supply noise of delay test during at-speed launch and capture is significantly larger compared to normal circuit operation since larger number of transitions occur within a short time frame. Our simulations have shown that for identical switching activity, a pattern with a short switching time frame window will surge more current from the power network, thereby causing higher IR-drop. In this paper, we propose a novel method to measure the average power of at-speed test patterns, referred to as switching cycle average power (SCAP).We present a case study of the IR-drop effects on design performance during at-speed test. A new practical framework is proposed to generate supply noise tolerant delay test patterns. The proposed framework uses existing commercial ATPG tools and a wrapper is added around them. The results demonstrate that the new patterns generated using our framework will significantly reduce the supply noise.

The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. These small delay defects might be activated on longer paths during functional operation and cause a timing failure. This paper presents an improved pattern generation technique for transition fault model, which provides a higher coverage of small delay defect that lie along the long paths, using a commercial no-timing ATPG tool. The proposed technique pre-processes the scan flip-flops based on their least slack path and the detectable delay defect size. A new delay defect size metric based on the affected path length and required increase in test frequency is developed. We then perform pattern generation and apply a novel pattern selection technique to screen test patterns affecting longer paths. Using this technique will provide the opportunity of using existing timing unaware ATPG tools as slack based ATPG. The resulting pattern set improves the defect screening capability of small delay defects.

Faster-than-at-speed test have been proposed to detect small delay defects. While these techniques increase the test frequency to reduce the positive slack of the path, they exacerbate the already well known issue of IR-drop during test. This may result in false identification of good chips to be faulty due to IR-drop rather than small delay defects. We present a case study of IR-drop effects due to faster-than-at-speed test. We propose a novel framework for pattern generation/application using any commercial no-timing ATPG tool, to screen small delay defects and a technique to determine the optimal test frequency considering both performance degradation due to IR-drop effects and positive slack.