With ever-larger scales of modern technology companies, it is necessary to be able to assign bugs found within organizations in a manner that is automated, accurate, and time efficient. Hence, an implementation of a bug triage, the process by which you assign bug cases, feature requests, and improvements to appropriate individuals and/or teams, has become a focus of many organizations. In this paper, we present, to the best of our knowledge, a novel data processing routine that has empirically shown to improve the baseline accuracy of various elementary classifiers. In most bug reports, there are discrete features, such as the nature of the bug and software environment details, and there are non-discrete features such as fluid error messages, comments, requests, etc. We perform principal component analysis on the one-hot encoded discrete features. Whereas, for the non-discrete features, we first use standard Natural Language Processing techniques to parse and tokenize the text and then employ a greedy variant of entropy-based keyword extraction. Moreover, we make use of a heuristic combination of the contributors (contribution weighted labeling) which is converted into a probability mass function, signifying the probability of assigning a case to a given individual. The results of such processing are profound, achieving state-of-the-art top-k accuracy. With the application of such data processing, our experiments show an average increase of 15% and 14%-points for team and developer assignments, respectively. Overall, we achieve Top-1 accuracy of 79%, Top-5 accuracy of 87%, and Top-10 accuracy of 90% for team assignments. As for developer assignments, we observe Top-1 accuracy of 54%, Top-5 accuracy of 63%, and Top-10 accuracy of 67%. These results were validated on a proprietary data set containing 257 teams and 2204 developers and show significant improvement in comparison to a previous study by our research group [1].

Bug tracking enables the monitoring and resolution of issues and bugs within organizations. Bug triaging, or assigning bugs to the owner(s) who will resolve them, is a critical component of this process because there are many incorrect assignments that waste developer time and reduce bug resolution throughput. In this work, we explore the use of a novel two-output deep neural network architecture (Dual DNN) for triaging a bug to both an individual team and developer, simultaneously. Dual DNN leverages this simultaneous prediction by exploiting its own guess of the team classes to aid in developer assignment. A multi-label classification approach is used for each of the two outputs to learn from all interim owners, not just the last one who closed the bug. We make use of a heuristic combination of the interim owners (owner-importance-weighted labeling) which is converted into a probability mass function (pmf). We employ a two-stage learning scheme, whereby the team portion of the model is trained first and then held static to train the team-developer and bug-developer relationships. The scheme employed to encode the team-developer relationships is based on an organizational chart (org chart), which renders the model robust to organizational changes as it can adapt to role changes within an organization. There is an observed average lift (with respect to both team and developer assignment) of 13%-points in 11-fold incremental-learning cross-validation (IL-CV) accuracy for Dual DNN utilizing owner-weighted labels compared with the traditional multi-class classification approach. Furthermore, Dual DNN with owner-weighted labels achieves average 11-fold IL-CV accuracies of 76% (team assignment) and 55% (developer assignment), outperforming reference models by 14%- and 25%-points, respectively, on a proprietary dataset with 236,865 entries.

Field-programmable gate arrays (FPGAs) commonly implement system architectures composed from soft-core configurable components, such as a cache with configurable size or associativity, a processor with configurable datapath units, or a configurable network-on-chip connecting dozens of processors. Configurable components increasingly exist even on pre-fabricated platforms. Tuning configurable components to the particular application running on the architecture and to particular design constraints represents a challenging task often left to a designer. Knowledge of the Pareto-optimal points of a system for particular applications can be of benefit to designers seeking to make appropriate design tradeoffs for given constraints. Previous methods for generating Pareto points required extensive knowledge of an architecture's parameter interdependencies, used a simplistic approach that failed to find many parameters, or used randomized search algorithms that may have long runtimes. We introduce an algorithm for finding Pareto points, based on statistically rigorous methods derived from the Design of Experiments paradigm and extended for the purpose of finding Pareto points. The resulting DoE-based Pareto point Generator, or DPG, algorithm finds thorough Pareto points while running 3 times faster than randomized search algorithms, without requiring designer knowledge of parameter interdependencies--in fact, the approach determines those interdependencies automatically, representing an added bonus. We demonstrate DPG on Platune's configurable processor-bus-cache system-on-chip, Noxim's configurable network-on-chip, and the configurable Microblaze FPGA processor.

Designing circuits for FPGAs involves challenges often distinct from designing circuits for ASICs. We describe efforts to convert a pattern counting circuit architecture, based on a pipelined binary tree and originally designed for ASIC implementation, into a circuit suitable for FPGAs. The original architecture, when mapped to a Spartan 3e FPGA, could process 10 million patterns per second and handle up to 4,096 patterns. The modified architecture could instead process 100 million patterns per second and handle up to 32,768 patterns, representing a 10x performance improvement and a 4x efficiency improvement. The redesign involved partitioning large memories into smaller ones at the expense of redundant control logic. Through this and other case studies, design patterns may emerge that aid designers in building high-performance efficient circuits for FPGAs

Parameterized components are becoming more commonplace in system design. The process of customizing parameter values for a particular application, called tuning, can be a challenging task for a designer. Here we focus on the problem of tuning a parameterized soft-core microprocessor to achieve the best performance on a particular application, subject to size constraints. We map the tuning problem to a well-established statistical paradigm called design of experiments (DoE), which involves the design of a carefully selected set of experiments and a sophisticated analysis that has the objective to extract the maximum amount of information about the effects of the input parameters on the experiment. We apply the DoE method to analyze the relation between input parameters and the performance of a soft-core microprocessor for a particular application, using only a small number of synthesis/execution runs. The information gained by the analysis in turn drives a soft-core tuning heuristic. We show that using DoE to sort the parameters in order of impact results in application speedups of 6times-17times versus an un-tuned base soft-core. When compared to a previous single-factor tuning method, the DoE-based method achieves 3times-6times application speedups, while requiring about the same tuning runtime. We also show that tuning runtime can be reduced by 40-45% by using predictive tuning methods already built into a DoE tool

Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are parameterized to support application-specific customization, wherein pre-defined units, such as a multiplication unit or floating-point unit, may be included in the microprocessor architecture to speed up software execution at the expense of increased size. We introduce a methodology for fast applicationspecific customization of a parameterized FPGA soft core, using synthesis and execution to obtain size and performance data in order to create a tool that can be used across a variety of tool platforms and FPGA devices. As synthesizing a soft core takes tens of minutes, developing heuristics that execute in an acceptable time of an hour or two, yet find near-optimal results, is

Soft-core programmable processors on field-programmable gate arrays (FPGAs) can be custom synthesized to instantiate only those hardware units, such as multipliers and floating-point units, that an application requires to meet performance demands, thus minimizing soft-core size on the FPGA. Conjoining processors, meaning to share hardware units among two or more processors, can further reduce soft-core size, leaving more resources for other circuits such as custom coprocessors. Using Xilinx MicroBlaze coprocessors and standard embedded system benchmarks, we show that conjoining two processors can provide 16% processor size reductions on average, with less than 1% cycle count overhead. We introduce an efficient dynamic-programming-based exploration method to find the best custom instantiation of hardware units, considering both standalone and conjoined options, for soft-core processors.