SRAM-based digital computing-in-memory (CIM) provides a low-power, high-precision method for multiply-and-accumulate (MAC) operations. However, input data with a high toggle rate and low sparsity will significantly increase the energy consumption of digital CIMs. This work presents an input-transforming and weight-precomputation (ITWP) SRAM-based digital CIM macro. Two strategies involving input sparsification and input restructuring are proposed to transform the dual-bit input data, resulting in higher sparsity and lower toggle rate. The sum of the weights is precomputed to correct the partial sum (PSUM) of the sparsified input data. A 13T-based hybrid SRAM CIM unit (HSCU) and a split adder tree (SAT) are proposed to compute on the restructured two input sets with different sparsity levels, leading to a higher throughput and energy efficiency. Finally, the ITWP CIM macro is implemented in a 28 nm process and achieves a peak throughput of 0.935 TOPS and an energy efficiency of 20.08-33.78 TOPS/W with signed 8b input and weight. Compared to the conventional bit-serial CIM macro, the ITWP CIM macro is demonstrated to increase the energy efficiency to 1.42x and up to 3.04x.

Accurate object counts represent essential semantical information in remote sensing imagery, significantly impacting applications like traffic monitoring and urban planning. Despite the recent advances in text-to-image generation in remote sensing, existing methods still face challenges in precisely controlling the quantity of object instances in generated images. To address this challenge, we propose a novel method, Multi-Grained Guidend Diffusion (MGDiff). During training, unlike previous methods that relied solely on latent-space noise constraints, MGDiff imposes constraints at three distinct granularities: latent pixel, global counting and spatial distribution. The multi-grained guidance mechanism matches the quantity prompts with object spatial layouts in the feature space, enabling our model to achieve precise control over object quantities. To benchmark this new task, we present Levir-QCG, a dataset comprising 10,504 remote sensing images across five object categories, annotated with precise object counts and segmentation masks. We conducted extensive experiments to benchmark our method against previous methods on the Levir-QCG dataset. Compared to previous models, the MGDiff achieves an approximately +40% improvement in counting accuracy while maintaining higher visual fidelity and strong zero-shot generalization. To the best of our knowledge, this is the first work to research accurate object quantity control in remote sensing text-to-image generation. The dataset and code will be publicly available at https://github.com/YZPioneer/MGDiff.

The recent advancement of generative foundational models has ushered in a new era of image generation in the realm of natural images, revolutionizing art design, entertainment, environment simulation, and beyond. Despite producing high-quality samples, existing methods are constrained to generating images of scenes at a limited scale. In this paper, we present MetaEarth - a generative foundation model that breaks the barrier by scaling image generation to a global level, exploring the creation of worldwide, multi-resolution, unbounded, and virtually limitless remote sensing images. In MetaEarth, we propose a resolution-guided self-cascading generative framework, which enables the generating of images at any region with a wide range of geographical resolutions. To achieve unbounded and arbitrary-sized image generation, we design a novel noise sampling strategy for denoising diffusion models by analyzing the generation conditions and initial noise. To train MetaEarth, we construct a large dataset comprising multi-resolution optical remote sensing images with geographical information. Experiments have demonstrated the powerful capabilities of our method in generating global-scale images. Additionally, the MetaEarth serves as a data engine that can provide high-quality and rich training data for downstream tasks. Our model opens up new possibilities for constructing generative world models by simulating Earth's visuals from an innovative overhead perspective.

High-performance analog and mixed-signal (AMS) circuits are mainly full-custom designed, which is time-consuming and labor-intensive. A significant portion of the effort is experience-driven, which makes the automation of AMS circuit design a formidable challenge. Large language models (LLMs) have emerged as powerful tools for electronic design automation (EDA) applications, fostering advancements in the automatic design process for large-scale AMS circuits. However, the absence of high-quality datasets has led to issues such as model hallucination, which undermines the robustness of automatically generated circuit designs. To address this issue, this article introduces AMSnet-KG, a dataset encompassing various AMS circuit schematics and netlists. We construct a knowledge graph with annotations on detailed functional and performance characteristics. Facilitated by AMSnet-KG, we propose an automated AMS circuit generation framework that utilizes the comprehensive knowledge embedded in LLMs. The flow first formulate a design strategy (e.g., circuit architecture using a number of circuit components) based on required specifications. Next, matched subcircuits are retrieved and assembled into a complete topology, and transistor sizing is obtained through Bayesian optimization. Simulation results of the netlist are automatically fed back to the LLM for further topology refinement, ensuring the circuit design specifications are met. We perform case studies of operational amplifier and comparator design to verify the automatic design flow from specifications to netlists with minimal human effort. The dataset used in this article is available at https://ams-net.github.io/ .

Chiplet-based systems have gained significant attention in recent years due to their low cost and competitive performance. As the complexity and compactness of a chiplet-based system increase, careful consideration must be given to microbump assignments, interconnect delays, and thermal limitations during the floorplanning stage. This paper introduces RLPlanner, an efficient early-stage floorplanning tool for chiplet-based systems with a novel fast thermal evaluation method. RLPlanner employs advanced reinforcement learning to jointly minimize total wire-length and temperature. To alleviate the time-consuming thermal calculations, RLPlanner incorporates the developed fast thermal evaluation method to expedite the iterations and optimizations. Comprehensive experiments demonstrate that our proposed fast thermal evaluation method achieves a mean absolute error (MAE) of$\pm 0.25$K and delivers over$120\mathrm{x}$speed-up compared to the open-source thermal solver HotSpot. When integrated with our fast thermal evaluation method, RLPlanner achieves an average improvement of 20.28% in minimizing the target objective (a combination of wirelength and temperature), within a similar running time, compared to the classic simulated annealing method with HotSpot.

This paper presents an accurate dB-linear programmable-gain amplifier with temperature-robust characteristic. A novel Gm-cell feedback topology is proposed to provide linear gain control as well as bandwidth extension without any extra power consumption. Moreover, a PTAT bias is employed to further promote the temperature robustness while AC coupling stages are embedded in the adjacent stages for DC-offset cancellation. Implemented in TSMC 65-nm CMOS technology, the proposed PGA exhibits a programmable gain range of 0 dB to 42 dB with 1 dB per step and 0.17 dB error. The gain variation across -40~125 °C is lower than 0.3 dB at all gain settings. The core circuit consumes a DC power of 3.8mV from a 1.2 V supply and occupies a layout area of 0.048 mm2.

In this paper, a fully integrated 24GHz integer-N PLL for a 60GHz wireless transceiver is presented. A VCO with tail-feedback technique is used to improve the phase noise by modulating the tail current, and a switched varactor array is also adopted together with a switched capacitor array to compensate the variation of KVCOover different bands. Moreover, benefiting from the careful optimization of CML pre-scaling divider, the PLL operates correctly when VCO buffer is turned off, coming up with an extremely low power. The whole PLL is fabricated in standard 90-nm process. Measurement shows that the VCO achieves a phase noise of -102dBc/Hz@1MHz offset with a tuning range of over 16%. The KVCOvariation over all bands is less than 16%. In close-loop operation mode the PLL shows an integrated phase error of 3.3°rms (from 100kHz to 100MHz) over prescribed frequency bands, and a total power dissipation of only 26mW.

A 60GHz receiver for 802.11ad application with superior performance in 90nm CMOS process, compared with prior arts in advanced processes, is proposed and realized. A 3-stage differential LNA achieves a gain of 19.8dB and a noise figure of 6dB in measurement, showing less than 0.3dB difference from simulation due to the elaborate consideration of parasitics. A baseband PGA with wideband and large gain tuning range is achieved from modified Cherry-Hooper amplifier with negative capacitive neutralization technique. The entire receiver achieves a double-side-band NF of 7.1dB and a maximal conversion gain of 64dB with 28dB tuning range, while consuming only 177mW of power. The measured output P1dBis -5.5dBm. All measured results are rigorously loyal to the simulation.

Al/W:AlOx/WOy/W and Pt/AlOδ/Ta2O5-x/TaOy/Pt multiple layers ReRAM devices have been fabricated and carefully studied. Experimental results exhibit significant performance improvement through the insertion of AlOxlayer between the switching layer and the top electrode. Operation current is remarkably reduced, ON/OFF ratio is greatly increased, and stable multi-level operations have been successfully achieved. Multiple layers stack engineering has been proved as an efficient method to improve the performances of ReRAM devices.

Finer grid representation is required for a more accurate description of mask patterns in inverse lithography techniques, thus resulting in a large-size mask representation and heavy computational cost. To mitigate the computation problem caused by intensive convolutions in mask optimization, a new method called convolution using basis expansion (CBE) is discussed in this paper. Matrices defined in fine grid are projected on coarse gird under a base matrix set. The new matrices formed by the expansion coefficients are used to perform convolution on the coarse grid. The convolution on fine grid can be approximated by the sum of a few convolutions on coarse grid following an interpolation procedure. The CBE is verified by random matrix convolutions and intensity calculation in lithography simulation. Results show that the use of the CBE method results in similar image quality with significant running speed enhancement compared with traditional convolution method.

In this paper, a wide-band inductor-less LNA for low voltage operation is presented. The input matching is implemented by using a feedback transistor with a resistor terminated to the source to enhance linearity and to reduce noise. Current reuse technique is employed to increase the total transconductance. Under 1V supply voltage and a DC of 5.6 mA, the LNA achieves an average noise figure of 3.2 dB, a maximum voltage gain of 18.6 dB, and 3 dB bandwidth ranges from 0.2-4.5 GHz.

Phase noise of oscillators can be improved through noise filtering. This paper presents a transformer-based harmonic filtering technique to improve the phase noise performance of the fully differential CMOS LC oscillators. The primary and secondary of the transformer are placed at the sources of NMOS and PMOS differential pairs, respectively. Due to the extra degree of freedom introduced by the transformer, the filter can resonate at two different frequencies, which are designed to be the second and fourth harmonics. The analysis of the filtering method is presented and principles of operation are discussed in details. The performance is compared with other filtering techniques, and the simulation results show improved FoM compared to published literature.

Power consumption has become a major concern since the integrated circuit industry entered the nanometer design regime. Due to the increasing process variation, deterministic leakage power analysis becomes inadequate and thus statistical analysis is required. The challenges of statistical leakage analysis are that the huge number of random variables make trivial computation of the variance inO(N2) time impractical for realistic designs and that knowing only the first two moments is not sufficient to obtain the distribution of the full-chip leakage. In this paper, we introduce efficient linear time algorithms for statistical leakage analysis. To enable those algorithms, a fast matrix vector product technique is crucial, being applied not only to compute the second moment of the total leakage, but also, combined with a comonotonic approximation, to estimate the distribution function of the total leakage power. The computational complexity of the proposed algorithms is provablyO(N), and the experimental result is presented with detailed discussion, indicating promising improvement in terms of accuracy.

With the continuous shrinking of the feature size, the effect of stress on the performance of the IC device and circuit can no longer be ignored. In fact, stress engineering is becoming more and more widely used today in advanced IC manufacture processes to improve device performance. Different from the intentionally introduced stresses to improve circuit performance, the shallow-trench-isolation (STI) stress, which is exerted by STI wells on the active area of devices, is a by-product of the fabrication process and has increasingly significant impact on the circuit behavior. This paper proposes a complete flow to characterize the influence of STI stress on the performance of RF/analog circuits by considering detailed layout and process information. An accurate and efficient finite-element method-based stress simulator has been developed to extract stress distribution from layouts of IC designs. The existing MOSFET model is also enhanced to capture the effects of stress on mobility, threshold voltage. With the enhanced model, we are able to study the influence of layout-dependent STI stress on the performance of real circuits and establish corresponding optimization strategies. The proposed flow has been applied to a series of RF/analog IC designs based on a 90-nm CMOS technology.

Random process variations are often composed of location dependent part and distance dependent correlated part. While an accurate extraction of process variation is a prerequisite of both process improvement and circuit performance prediction, it is not an easy task to characterize such complicated spatial random process from a limited number of silicon data. For this purpose, kriging model was introduced to silicon society. This work forms a modified kriging model with L1-norm penalty which offers improved robustness. With the help of Least Angle Regression (LAR) in solving a core optimization sub-problem, this model can be characterized efficiently. Some promising results are presented with numerical experiments where a 3X improvement in model accuracy is shown.

Passivity enforcement is an important issue for macro-modeling for passive systems from measured or simulated data. Existing convex programming based methods are too expensive and thus are ruled out for realistic application. Other methods based on iteratively fixing the passivity through perturbing the eigenvalues of the Hamiltonian matrix either suffer from convergence issue or lack optimality which will sometimes lead to unacceptable error. In this paper we propose a novel framework for macro-modeling. In addition to the traditional two-stage (fixing plus enforcement) schemes, we propose a post-enforcement optimization, which takes a passive, while potentially not-so-accurate model, as the starting point, and performs local search to find the local optimum with passivity constraint or build-in passivity guarantee. A simple yet stable passive modeling generator is proposed to produce the starting model for optimization. Two algorithms are proposed for performing constrained and unconstrained optimizations. Experiments show that the accuracy of passivity-fixed model can be significantly improved with the proposed methods.

This paper presents a full ESD-protected receiver front-end for wireless communications around 24GHz, comprising LNA, mixer, VGA, and on-chip balun. A π -type input matching network incorporating ESD capacitance is constructed to realize the source impedance transformation for higher gain. With it, the gain of the first stage is improved while the noise figure is just degraded slightly. The measured results show an input return loss of less than-12dB, 36dB voltage gain, 6.9dB noise figure, and 2dBm output P1dB. The chip has an HBM ESD robustness of ± 2kV and consumes 34mA from a 1.2V supply with a total area of 1×0.8 mm2using 0.13μm RF CMOS process.

An analytical framework has been developed to describe the locking behavior of millimeter (mm) wave current mode logic (CML) frequency divider. Unlike traditional analysis based on RC delay, the proposed model is established with injection-locking concept from analog perspective. Both analytical formulas and graphic interpretation are provided for design insights. The model has been validated by exhaustive simulations and important guidelines have been concluded for circuit design.

Source and mask optimization (SMO) has been proposed recently as an effective solution to extend the lifespan of conventional 193 nm lithography, although the process is computationally intensive. In this study, we propose a highly effective and efficient method for source optimization and improve a previous method for mask optimization. An SMO framework is implemented by integrating them. Based on pixel-based source and mask representation, the gradients of the objective function are utilized to guide optimization. In addition to maintain the image fidelity, extra penalties are added into the objective function to increase the depth of focus (DOF) and regularize the source and mask patterns. In our SMO framework, a specially designed mask optimization procedure is performed to enhance the algorithm robustness. Afterward, the source optimization and mask optimization are performed alternatively. Convergence results can be acquired using only two or three iteration cycles. This method is demonstrated using two mask patterns with critical dimensions of 45 nm, including a periodic array of contact holes and a cross gate design. The results show that our method can provide great improvements in both image quality and DOF. The robustness of our method is also verified using different initial conditions.

A robust pixel-based optimization algorithm is proposed for mask synthesis of inverse lithography technology (ILT) to improve the resolution and pattern fidelity in optical lithography. Result shows that the final image fidelity is almost independent of the initial condition. To demonstrate the robustness of the algorithm, six typical desired mask patterns and two mask technologies are applied in mask synthesis optimization using 100 randomly generated initial conditions. The critical dimension (CD) is 60nm and the partial-coherence image system is applied. It is found that the final edge placement error (EPE) and iteration number are quite weakly dependent on the initial conditions. Good final image fidelity can be acquired using arbitrary initial conditions. This algorithm is about several orders of magnitude faster and more effective than other gradient-based algorithm and simulated annealing algorithm.

Existing approaches to statistical leakage analysis focus only on calculating the mean and variance of the total leakage. In practice, however, what concerns most is the tail behavior of the sum distribution, as it tells that to what extent the design will be safe or reliable. However, computing the tail distribution is much more difficult than computing the mean and variance. In this paper, we tackle this problem by making use of the recent developments in the area of financial and insurance analysis, as well as the fast evaluation algorithm for the variance of spatially correlated random sums. The proposed algorithm is provably of O(N) complexity. Experiments show that the algorithm provides 1% accuracy in modeling the tail behavior and it is 10X more accurate compared with existing methods that approximate the distribution by matching the moments of a lognormal distribution.

A new compact model for the substrate network of RF MOSFETs with deep n-well (DNW) implantation is presented. A novel test structure proposed in is employed to directly access the characteristics of the substrate in two-port measurements for the extraction of substrate network components. A method is developed to analytically extract the parameters for the substrate network from two-port measurements. The methodology is verified and validated by the excellent match between the measured and simulated output admittances for a 64-finger DNW n-MOSFET in common-source configuration.

With the continuous shrinking of feature size, various effects due to shallow-trench-isolation (STI) stress are becoming more and more significant. The resulting nonuniform distribution of stress affects the MOSFET characteristics and hence changes the circuit behavior. This paper proposes a complete flow to characterize the influence of STI stress on performance of RF/analog circuits based on layout design and process information. An accurate and efficient FEM-based stress simulator has been developed to handle the layout dependence. A comprehensive MOSFET model is also proposed to capture the effects of STI stress on mobility, threshold voltage, and leakage current. The influence of layout-dependent STI stress on the circuit performance is further studied, and the corresponding optimization strategies to circuit design are discussed. A realistic PLL design realized using 90nm CMOS technology is used as a test case for the proposed approach.

Statistical full-chip leakage analysis considering spatial correlation is highly expensive due to its O(N2) complexity for logic circuits with N gates. Although efforts have been made to reduce the cost at the loss of accuracy, existing methods are still unsuitable for large-scale problems. In this paper we resolve the problem by re-formulating the computation to one that can be done efficiently using a well-developed technique that has been widely used in fast EM simulation and machine learning areas. The resulting algorithm is provably of O(N) or O(N log N) complexity with well-defined and easily-controlled error bounds. Experiments show that using the proposed method it is feasible to handle milliongate circuits within only a few minutes on a regular desktop PC. The corresponding error is less than 0.5% compared to exhausted computation that takes more than 3 days. The proposed method is about 300X faster and 10X more accurate compared to existing grid-approximation method.

In this paper, we describe the algorithms implemented in MBEM, a program for wideband impedance extraction of complicated 3-D structures. MBEM is based on a mixed boundary element method (BEM), which reduces the number of unknowns from about 7N in FastImp to 4N, for MQS analysis. Efficient techniques are proposed to handle the extra matrix multiplication, form post-process matrices, and solve the final linear equation system. The inaccuracy of calculation using FastImp at low frequency is also analyzed, which shows the mixed BEM eliminates it completely. Experiments on several typical 3-D structures validate the advantage of MBEM over FastImp, on both accuracy and efficiency.

In this paper, a methodology for full-chip leakage analysis based on accurate modeling of different leakage currents in nano-scaled MOSFETs has been developed. Novel process effects have been covered in our statistical model, and a systematic characterization method of leakage-related parameter variations has been proposed. With these two contributions, we present an effective algorithm to address the growing issue of full-chip leakage verification for actual-fabrication circuits. Unlike many traditional approaches that rely on log-Normal approximations, the proposed algorithm applies a quadratic model of the logarithm for the full-chip leakage current and is able to include both Gaussian and non-Gaussian parameter distributions. Our simulation examples in a 65 nm CMOS process demonstrate that the proposed methodology provides more accurate results compared with the previous methods, while achieving orders of magnitude more efficiency than a Monte Carlo analysis.

An efficient method is proposed to consider the process variations with spatial correlation, for chip-level capacitance extraction based on the window technique. In each window, an efficient technique of Hermite polynomial collocation (HPC) is presented to extract the statistical capacitance. The capacitance covariances between windows are then calculated to reflect the spatial correlation. The proposed method is practical for chip-level extraction task, and the experiments on full-path extraction exhibit its high accuracy and efficiency.

An efficient algorithm based on the pixel-based mask representation is proposed for fast synthesis of model-based inverse lithography technology (ILT) to improve the resolution and pattern fidelity in optical lithography. This new algorithm reduces N2intensity computations to three (3) equivalent intensity computations per iteration, where N2is the total number of pixels in a mask. This algorithm has been demonstrated using different critical dimensions (CDs) and different mask technologies with incoherence and partial-coherence image models. This algorithm is about 60 times faster and more effective than the current gradient-based algorithm. The final image fidelity has quite a weak dependence on the initial condition. Good fidelity images are achieved when CD is reduced to 45 nm.

In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent total leakage power of a large circuit block, considering Ijunc, sub-threshold leakage (Isub), and gate oxide leakage (Igate). We then propose our algorithm to estimate the full-chip leakage power with consideration of both Gaussian and non-Gaussian parameter distributions, capturing spatial correlations using a grid-based model. Experiments on ISCAS85 benchmarks demonstrate that the estimated results are very accurate and efficient. For a circuit with G gates, the complexity of our approach is O(G).

An efficient algorithm for three-dimensional (3-D) capacitance extraction on multi-layered and lossy substrate is presented. The new algorithm represents a major improvement over the quasi-3D approach used in Green's function-based solvers by taking into consideration of the side-wall effects of the conductors. The accuracy and efficiency of the new algorithm is tested by examples.

The notion of design for manufacturability is blurring the separation between the tasks of design and manufacture. In the era of nano-technologies, the description of the design rules has retreated back to an early stage form of many conditional cases and even an art. Thus, it is important to set the metrics for the manufacturability. However, who is going to be held accountable for the final outcomes? Should the designer, the EDA developer, the manufacture engineer, or a new breed of experts take the lead to tackle the problem?

A new model for spiral inductors, which covers wide operation frequency range and full design parameters, is proposed by using artificial neural network (ANN). It is pointed out that a four-layered neural network is superior to a three-layered neural network both on the mapping and generalization abilities in spiral inductor modeling. For the first time, a novel physics-based sampling technique is adopted in modeling procedure. Equipped with this new sampling method, ANN model achieves better speed and accuracy performances though the training data are substantially reduced. The new sampling method can be easily applied to other passive components and be embedded in various modeling frameworks.

A new analytical current-voltage (I-V) model for submicrometer and deep-submicrometer metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed based on a newly developed charge-control model for the metal-oxide-semiconductor structure. Threshold-voltage shift due to quantum mechanical effects, finite inversion layer thickness effects (inversion layer capacitance), as well as increased depletion layer charge density after the strong inversion point are incorporated in the model. Inversion layer charge density with respect to the gate voltage from depletion through weak inversion to strong inversion regions with smooth transition between different regions is given by one expression. Two-dimensional short channel effects such as channel length modulation, drain-induced barrier lowering, mobility degradation, and carrier velocity saturation, as well as polysilicon depletion effects are included in the I-V model. Model results are compared with both numerical results of carrier sheet density and surface potential in the channel, and experimental results of I-V data for submicrometer and deep-submicrometer MOSFETs down to 0.09-/spl mu/m effective gate length and the accuracy of the model are demonstrated.

Harmonic and intermodulation distortion effects play an important role in numerous analog applications, particularly in such areas as wireless communication systems. In this paper, we present a two-dimensional harmonic balance semiconductor device simulator which accurately models these nonlinear effects at the physical (drift-diffusion) level. The simulator is based on Stanford University's PISCES code, and supports the full range of physical models and features present in the time-domain version of the program. A modified block Gauss-Seidel-Newton nonlinear relaxation scheme is developed to efficiently handle the extremely large size of two-dimensional harmonic balance semiconductor device simulation problems.

A scheme for automated tracing of arbitrarily shaped I-V curves is presented. Tracing out the I-V curves for complicated device phenomena such as breakdown in bipolar transistors and latchup in CMOS structures using conventional device simulation techniques requires a priori knowledge of the shape of the I-V curve and thus is not suitable for exploring new device phenomena. This paper presents a dynamic load-line technique which adapts the boundary conditions as the trace progresses to ensure convergence. By monitoring the slope of the curve, an optimal boundary condition is determined for each point. The boundary condition consists of a voltage source and load resistance corresponding to a load line which is orthogonal to the differential resistance at each point. This orthogonality is defined in a coordinate system scaled by the DC resistance. Step size between points is also defined by this scaling and is varied according to a smoothness criterion. The algorithm guarantees fully automatic tracing of any I-V curve without prior knowledge of the curve's characteristics. Its implementation is completely external to the device simulator, i.e., it simply sets up the boundary conditions to be used by the simulator. Curve tracing examples which validate the algorithm are discussed.>

A robust numerical model for the charge balance condition (CBC) on floating gates (FG) is presented, in which the quasi-Fermi level, instead of the potential (as in conventional models), is assumed to be a constant in the FG. By solving Poisson's equation in the FG region with an extra equation for the CBC, the accurate distribution of both potential and charge can be obtained. A quasi-stationary scheme is developed to simulate the writing or erasing procedure of EEPROM cells, which may serve as a useful tool for accurate simulation of devices such as EEPROMs or EPROMs. Simulation results reveal a significant degradation of tunneling efficiency when N/sub FG/>

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An accurate method of simulating nonequilibrium gate current and sheet-carrier concentration in AlGaAs/GaAs HEMT structures is reported. The calculation is based upon self-consistent solving of Schrodinger's equation, Poisson's equation and continuity equations. A concept for three-dimensional electrons accompanied by two-dimensional electrons in a quantum well at a heterointerface makes it possible to solve the continuity equation at the quantum-well region. Thermionic emission theory is applied for the current expression across an abrupt heterointerface. As a result, there is a certain voltage drop across the heterointerface, which helps prevent the creation of the neutral region in the AlGaAs layer. Simulated results explain measured gate-current and channel-conductance characteristics of a HEMT structure.>

A novel algorithm based on the Newton projection scheme [1] is proposed to improve the convergence behavior of circuit simulation. The computation experiment shows that the number of iterations to achieve convergence in Newton-Raphson method can be cut by as much as twenty nine-fold, and the convergence behavior of the Newton iteration is made much more robust using this algorithm. Moreover, the implementation of the proposed algorithm in conventional circuit simulators such as SPICE is very easily done. Both the theoretical background and actual implementation of the algorithm are discussed. The experimental circuit and simulation results are also shown.

The Newton iteration method used in conventional numerical device simulations is extended to include bias conditions as variable parameters in the system of semiconductor equations. This extension leads to a very simple algorithm to evaluate low-frequency, small-signal parameters based on dc solutions. It also provides an elegant way to project an initial guess for subsequent bias conditions. Rigorous mathematical derivation and applications to the evaluation of junction capacitance and breakdown voltage are given. The initial guess projection is also illustrated through examples.