In this paper, A CMOS voltage reference (CVR) with two-stage self-biased stacked diode connected MOS transistors (SDMTs) which actively compensates for process, voltage, and temperature (PVT) variations via a tandem differential structure (TDS) is proposed. The SDMTs core biased by new pseudo cascode current mirror guarantees better suppression against supply change and generates two reference voltages. The TDS, composed of two tandem NMOS transistors, serves as an output stage, differentially processing these voltages and compensating the final reference against PVT variations. Thus, the deviation of final reference voltage from PVT change is largely reduced. The proposed CVR is fabricated in a 0.18-$\mu $m CMOS process occupying a total area of$0.0048~\mathbf {mm^{2} } $. Measurement results from 7 chips demonstrate that the design can achieve an average temperature coefficient of 67 ppm/° C from −40° C to 140° C without trimming networks. Line sensitivity and power supply rejection ratio are 0.009 %/V with a supply range of 1.3V to 2.5 V and -83 dB at 100 Hz. 1% settling time only takes 0.28ms. The average reference voltage is 294 mV.

This brief presents an ultralow-energy and low-propagation-delay balanced voltage level shifter (VLS) with a wide voltage conversion range. The proposed VLS achieves low propagation delay while operating with subthreshold voltage, utilizing a newly introduced dynamic biasing scheme (DBS). This scheme improves both turn-on and turn-off speeds by reducing the threshold voltage of the input device circularly. The biasing-related power consumption is largely reduced by well-designed structure. The function of the proposed VLS design has been validated by using a standard 130-nm CMOS technology, taking into account process, voltage, and temperature (PVT) variations. With the implementation of the DBS, the delay is reduced to 6.5 ns, dynamic energy is lowered to 21.7 fJ, the minimum supply voltage is 0.18 V, and the average static power consumption is 2.8 nW for a conversion from 0.3 to 1.2 V.

This addresses errors in the Early Access version of [1]. Due to a publisher error, the terms Q1, Q2, and Q3 were used (with subscripts) instead of Q1, Q2, and Q3 (no subscript). They represent nodes on the schematic, not variables.