This article presents a 2-by-2 multiple-input multiple-output (MIMO) transceiver array operating at 28 GHz to enable fifth-generation (5G) new radio (NR) communication, which is an extended work of the article. It employs transformer-based inter-stage matching, with a comprehensive analysis of its benefits and challenges. To mitigate the transformer’s impedance imbalance peaks across frequency, two gain equalization techniques are proposed, thoroughly analyzed, and implemented in both the transmitter (Tx) and receiver (Rx). Fabricated in TowerSemi’s$0.18~\mu $m BiCMOS process, the chip achieves a power consumption of 93 mW (Rx) and 146.5 mW (Tx), with gains of 20 and 19 dB, respectively. Additionally, design considerations for a high-performance RF switch and a wideband Wilkinson power combiner/splitter are discussed.

A 2-by-2 MIMO transceiver array operating at 28GHz that enables the 5G New Radio (NR) communication is presented. To achieve a flatter and wider bandwidth for both transmitter (TX) and receiver (RX), a novel transformer-based passive matching networks is analysed and implemented on chip. The chip was fabricated in the TowerSemi 0.18μm BiCMOS process and achieves a RX/TX mode power consumption of 93mW/146.5mW, with a gain of 20/19dB respectively. In addition, the design considerations for the high-performance RF switch and the wideband Wilkinson power combiner/splitter are presented.

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

A 28-GHz one-bit direct-detection based MIMO receiver with wireless LO distribution is presented. Unlike a conventional MIMO structure, in this work the antenna receives both RF and the broadcast single-ended LO, and directly converts them to an IF signal by using a simple low-power square-law detector without the need for a conventional mixer or LO buffers. An LNA with a notch filter is designed to help reduce the non-idealities that appear when the input LO power is lower than that of the RF. A 1-GS/s symbol rate with a high error-vector magnitude is achieved with a power consumption of 33 mW by using a 0.18um SiGe BiCMOS process.

Spin transfer torque (STT-RAM) is a fast, scalable and non-volatile memory technology. These characteristics make STT-RAM one of the best candidates among memories that can be used for space applications. Although STT-RAM cell itself is immune to high energy particles, its sensing circuit might be severely affected by radiation. In this work, we first extensively analyze the effect of radiation on the STT-RAM sense circuit and then propose a radiation hardened circuit. Using a dual modular redundancy and a voting scheme, radiation susceptibility of the sense circuit is eliminated. The sense circuit is implemented in 45 nm CMOS technology. Simulation results show that the proposed circuit is immune to radiation pulses up to 400 Krad.

A hybrid equalizer architecture based on asynchronous sampling for serial backplane links is described. The equalizer incorporates a continuous-time linear equalizer for the main tap and five digital post-cursor taps combined into a hybrid feed-forward equalizer (FFE) structure. Level-crossing samplers and inverter-based delay lines are used to construct the digital taps. This approach eliminates the need for high-speed clock generation and data recovery. The simulated performance using 40nm CMOS technology demonstrates 3.18 pJ/bit power efficiency while achieving data reception through 30 dB Nyquist insertion loss at 28.57 Gbps NRZ data rate.

TSV-to-TSV coupling is known to be a significant detriment to signal integrity in three-dimensional (3D) IC architectures. Designing a reliable Through-Silicon Via is critical in order to support better performance. This paper explores the challenges brought on by capacitive and inductive TSV-to-TSV coupling in TSV-based 3D ICs. Based on our analyses, we propose two approaches to mitigate these effects. In one approach, a novel coding technique that adjusts the current flow pattern is proposed to mitigate the inductive coupling effects. In another approach an alternative architecture, wrapping around the TSVs, is proposed to greatly reduce the capacitive coupling effect. The efficiency of the proposed coding methods and supporting architectures is demonstrated by comprehensive simulations at both the hardware and system levels.

A charge integrator is an essential building block used in time-based ADCs and sensor readout circuits. In this paper, time-domain noise analysis is used to calculate the effect of all noise sources, including 1/f noise, on the voltage noise variance of the integrator. The results show that for short charge integration intervals, the contribution of 1/f noise sources to the total voltage variance of the integrator is not significant. Different design trade-offs for optimally choosing the capacitance of the integrator and current mirror ratio are discussed. The accuracy of the developed equations is verified by transient noise simulations.

A 2 × 50 Gb/s receiver with adaptive channel loss equalization and crosstalk cancellation is proposed using a SiGe BiCMOS process with an fTof 200 GHz. The channel loss equalizer is realized using a feedforward equalizer (FFE), and the crosstalk canceller (XTC) is realized using a current-mode summer. The XTC adaptation makes use of a signal provided by the clock/data recovery (CDR) circuit. The entire receiver is estimated to dissipate 290 mW from a 2.0 V supply, translating to 2.9 pJ/bit, and increases the horizontal eye opening by up to 77%.

It is shown how a continuation method can be used to verify the effectiveness of startup circuitry used in bootstrapped circuits to avoid the zero current state. In particular, the curve generated by such a continuation method can be used to assess the robustness of the startup circuitry.

The design of distributed amplifiers in a CMOS process is investigated. In particular, the impact of parasitic elements from the transistors and from interstage inductors is studied. A methodology for determining an optimum design, including the number of stages, without needing a complete inductor model at the outset, is presented. This proposed methodology reduces the time and complexity of a distributed amplifier design while at the same time allowing the designer to gain more insight into the circuit's behavior.

The assumption that the white noise sources independently affect the phase noise and jitter in ring oscillators is revisited. Propagation of jitter originating from a noise source around the ring oscillator loop and its effect on phase noise are quantified. It is shown how, contrary to the commonly-held assumptions, the resulting jitter can in fact depend on the number of stages.

The design of CMOS current-mode logic (CML) logic gates is discussed. A novel CML transistor-only topology that realizes an active inductive load is presented. This topology makes use of thicker oxide transistors often available in standard CMOS processes and an additional, higher, supply voltage that does not conduct any dc current. It is shown by simulation results that this topology provides favorable dc biasing compared to existing techniques while exhibiting better performance.

Dual inverter based ring oscillators are revised for better use of current and higher achievable frequency of operation. Analysis of their close-in 1/f3region phase noise has been presented and compared with measured and simulated results

The use of continuation methods has been shown to be more effective than standard Newton-Raphson-based methods in finding the operating point(s) of circuits possessing multiple operating points or in dealing with circuits exhibiting convergence problems in DC. In this paper we propose a method of dealing with numerical problems caused by a singular or nearly singular Jacobian matrix along a zero curve resulting from the use of a continuation method. This method has been implemented in a circuit simulator that uses a continuation method. Using the implementation we were able to achieve a much better convergence rate for some circuits. The proposed method is not limited to simulators based on homotopy methods only; it can be used with any ODE solution algorithm based on a predictor-corrector mechanism. Several circuit examples are given.

A CMOS variable-gain amplifier that works down to V/sub DD/=1.5 V is described. The gain characteristic is arranged to be a nearly exponential function of control voltage by a novel circuit topology that utilizes triode-biased transistors in pseudo-differential configurations. This circuit is designed using a 0.35 /spl mu/m CMOS process and operates at a 3-dB frequency of 21 MHz with a maximum power consumption of 24.8 mW.

A general method is given for finding conditions guaranteeing that when a single transistor is replaced by a small subcircuit, the uniqueness of the circuit's operating point will be retained. Use of this method is illustrated on circuits containing compound transistors (Darlington pairs), current mirrors and cascodes. With this method it is possible to build a "library" of subcircuits that can be replaced by a single transistor for purposes of applying the Nielsen-Willson Theorem.

A sufficient condition is given for which a continuation method is guaranteed to find at least three operating points possessed by a multistable circuit. A practical realization of this condition in a homotopy using passive components is also given and demonstrated in circuit examples.

An error amplifier for use in a DC power supply control circuit is described. The amplifier is designed using a loser-take-all control structure in order to implement both current and voltage control of the the power supply output.

The standard SPICE dc operating point analysis does not distinguish between stable and unstable operating points. Circuit designers can be misled when an operating point "looks" correct on the basis of dc simulation but turns out to be unobservable once the circuit is breadboarded or fabricated. The algorithm presented herein can identify a large class of unstable operating points, and it has been incorporated into the SPICE dc operating point analysis without compromising analysis speed.>

A current-mode implementation of a frequency-dependent negative resistance (FDNR) element is presented using a novel capacitive gyrator. This FDNR element lends itself well to the design of low-pass ladder filters and its use will result in a more efficient integrated circuit implementation than filters that simulate floating inductors using resistive gyrators.>

A new transconductance block with four inputs and two outputs is presented. It is shown that fully differential circuits using this block can be built without the requirement of common-mode feedback.>