Motivation: Polypeptide sequence length is the single dominant factor hampering the effectiveness of currently available software tools for de novo calculation of amino acid-specific protonation constants in disordered polypeptides. Results: We have developed pepKalc, a robust simulation software for the comprehensive evaluation of protein electrostatics in unfolded states. Our software completely removes the limitations of the previously reported Monte-Carlo approaches in the computation of protein electrostatics by using a hybrid approach that effectively combines exact and mean-field calculations to rapidly obtain accurate results. Paired with a modern architecture GPU, pepKalc is capable of evaluating protonation behavior for an arbitrary-size polypeptide in a sub-second time regime. Availability and implementation: http://protein-nmr.org and https://github.com/PeptoneInc/pepkalc.

EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOORIST) and a database (DATABIST). EXIST contains several unique features including: editing while in simulation, manual and automated hierarchical floorplan optimization, and user-friendly interface based on the model-view controller paradigm of Smalltalk. These features make EXIST a promising environment for exploration of alternative VLSI architectures, such as RISC (reduced instruction-set computer) controllers.>

A functional simulator/editor for VLSI design has been implemented in the Smalltalk-801 system. Users can explore their designs in an highly interactive and graphical manner with “close-to-reality” tools. The traditional sequence of editing, compiling and simulating the circuit is avoided. During editing, functional Modules can immediately respond to new connections. The simulator, called INSIST, strongly supports hierarchical simulation and design up to gate level. Hardware descriptions of the design can be generated for other CAD systems. From these descriptions layout has been generated. A RISC chip was entered and simulated at three hierarchical levels containing more than 50 Modules.