Power optimization can reduce heat dissipation costs and has become an important step of circuit logic synthesis. Because the power optimization for mixed polarity Reed–Muller (MPRM) circuits is a combinatorial optimization problem, in this paper, we first propose a multilevel adaptive memetic algorithm (MAMA), which includes global exploration optimizer, local heuristic optimizer, and initial population optimizer. We use the proposed differential evolution optimization, simulated annealing optimization, and data matching algorithm to make the population evolve. Moreover, based on the proposed matrix decomposition strategy and parallel polarity conversion algorithm, we propose a power optimization approach (POA) for MPRM circuits, which searches for an MPRM circuit with a minimum power using the MAMA. Experimental results demonstrated the effectiveness and superiority of the POA in optimizing the power of MPRM circuits.

Area optimization is one of the most important contents of circuits logic synthesis. The smaller area has stronger testability and lower cost. However, searching for a circuit with the smallest area in a large-scale space of polarity is a combinatorial optimization problem. The existing optimization approaches are inefficient and do not consider the time cost. In this paper, we propose a multi-strategy wolf pack algorithm (MWPA) to solve high-dimension combinatorial optimization problems. MWPA performs global search based on the proposed global exploration strategy, extends the search area based on the Levy flight strategy, and performs local search based on the proposed deep exploitation strategy. In addition, we propose a fast area optimization approach (FAOA) for fixed polarity Reed-Muller (FPRM) logic circuits based on MWPA, which searches the best polarity corresponding to a FPRM circuit. The experimental results confirm that FAOA is highly effective and can be used as a promising EDA tool.

With the emergence of the multicore architecture and the increase of chip operating frequency, power optimization has become a key step of circuit logic synthesis. Aiming at the XNOR/OR circuits, with the goal of minimizing power, construct the optimal polarity fixed-polarity Reed–Muller (FPRM) circuits power optimization scheme. However, the power optimization for FPRM circuits is a multipeak combinatorial optimization problem, we first propose a metaheuristic optimization algorithm (MOA), which includes the global exploration optimizer, local deep exploitation optimizer, and initial population and uses the proposed differential evolution optimization, fierce wolf siege algorithm-based tabu search, and improved skew tent map to make the population evolve. Based on the proposed Huffman tree construction algorithm and MOA, we propose an efficient power optimization approach (EPOA) to find the minimum power FPRM circuit. Experimental results on the benchmark circuits confirm the effectiveness of EPOA.